Dong Wang

This work presents the first fully integrated Ka-band all-digital outphasing transmitter-based IC for bit-to-RF multibeam digital beamforming (DBF) arrays. To enhance the design flexibility of digital systems operating at millimeter-wave (mmWave) frequencies, this work employs an outphasing architecture that facilitates signal digitization in the phase domain as opposed to the amplitude domain. The $LC$ -based injection-locked oscillator (LC-ILO) digital phase modulator (DPM) and the quadrupler are adopted to provide the constant envelope modulated signals. The proposed quadrupler lowers the operating frequency and reduces the phase shifting range to 90°, which allows the DPM to work in a better linear range. For high intrinsic linearity, a piecewise varactor array (PVA) linearization technique is used in the DPM of the DTX, and an rms phase error of 0.38°–0.75° is achieved in the 90° phase range under 6–8GHz. Furthermore, an all-digital phase-locked loop (ADPLL) is integrated to reduce the clock distribution complexity by operating from a high radio frequency (RF) to a reference frequency. With these techniques, a low-cost 24.5–30-GHz DTX is fabricated in 40-nm CMOS and occupies a compact core area of $1.2\times 1.35$ mm². Abit-to-RF concurrent multibeamforming for three independent beams is demonstrated with a $1\times 8$ uniform linear array (ULA) demo. It achieves state-of-the-art normalized energy and area efficiency, consuming only 53mW per beam per element and 0.54mm² per beam per element.

This article presents a wideband receiver (RX) operating in 10–72 GHz with multiprotocol coverage, which integrates the inductor-less local oscillator (LO) frequency quintupler for down-mixing. In the LO generator, phase interpolators (PIs) are implemented to obtain five-phase pulses. Then compact edge-combining switched-capacitor (SC) based frequency quintuple techniques are proposed to output LOs ranging from 10 to 40GHz while operating within the 2–8 GHz frequency range. The lower input frequency brings lower driving difficulty, higher I/Q precision, and better phase noise performance. Therefore, based on the LOs orthogonality accuracy and IQ calibration, the baseband phase shifter (PS) with lower power and die area consumptions is applied in the receiver. For the 40–72 GHz channel, the RF signals are down-mixed two times with the same LO frequency to reduce the quintupled LO frequency to f_RF/2. By folding the image band to DC during the first down-mixing, an image rejection ratio (IRR) exceeding 100 dB is achieved through the input-matching transformer of LNA, thus eliminating image interference and flicker noise introduction. Fabricated in 40-nm CMOS technology, the proposed RX features a core area of 0.9mm², a conversion gain of over 45 dB, an output IP3 of over 19.7 dBm, and the noise figures (NFs) lower than 6.1, 6.9, and 8.7 dB in the 10–18 GHz, 18–40 GHz, and 40–72 GHz bands, respectively.

This article presents a transmitter (TX) and receiver (RX) system operating in the 0.1–6 GHz frequency range with multi-protocol compatibility, which integrates local oscillator (LO) harmonic rejection (HR) radio frequency front-ends (RFFE) spanning 0.1–2.5 GHz, with frequency-adaptive calibration capabilities. In the HR-RFFE, programmable RC networks are deployed in both the TX and RX to achieve intermediate frequency (IF) domain HR and pre-calibration. An 8-phase LO signal generation, utilizing a D flip-flop (DFF) based chain, is employed to facilitate HR calibration. To mitigate HR degradation caused by LO phase errors, the TX employs a cross-connected Gilbert phase detector (PD) to assess the orthogonality of 90$^{\circ}$ shifted LO signals, enabling LO calibration. For the receiver, phase errors are directly calculated via the baseband (BB) output at a much lower frequency. Fabricated in 40-nm CMOS technology, the TX features a core area of 1.2 mm², a programmable gain range of -12–26 dB, a P1dB compression point of 16.1 dBm, and a system efficiency of 25.9%. The third and fifth harmonic rejection ratios (HRRs) exceed 46.9 and 53.5 dBc, respectively. The receiver, which incorporates an integrated ADPLL, shows a core area of 1.4 mm², a maximum gain of 68.4 dB, a minimum noise figure of 3.9 dB, and an odd-order HRR exceeding 71 dBc.

This paper presents a 2.85-mm $^{2}$ 0.4-6 GHz RF transceiver in 40-nm CMOS for low-cost and low-power IoT micro-hub applications. A single-path receiver (RX), an all-digital phase-locked loop (ADPLL), and a digital transmitter (DTX) (including a digital power amplifier, DPA) are integrated. In the RX, to reduce the chip area and power consumption, an inductor-less capacitive-feedforward wideband LNA and a Gm-C filter-based dc offset cancellation (Gm-C-DCOC) technique are proposed. The RX achieves a noise figure (NF) of 1.3-4.9 dB over 0.4-6 GHz while consuming 31 mW. The measured average IIP3, in-band P1dB, and calibrated IIP2 of the receiver are 4.5 dBm, $-$ 13.8 dBm, and 67.5 dBm, respectively. In the ADPLL, a calibration-free retiming fractional frequency dividing (FFD) scheme based on a parasitic insensitive digital phase interpolator is adopted, for releasing the narrow loop bandwidth limitation and achieving better phase noise without active noise cancellation techniques. In the DTX design, a piecewise bias voltage (PBV) technique is proposed for the AM-AM linearization. It achieves a peak output power of 22.5 dBm at 840 MHz with a drain efficiency of 60.2%. The DPA can work in a high-power mode without PBV and a middle-power mode with PBV for modulation with different complexity. Thanks to PBV, the DTX achieves 5.9%, 5.3% EVM for 2MS/s 16-QAM and 64-QAM without digital pre-distortion (DPD), respectively. The designed broadband reconfigurable transceiver can support most of the common IoT protocols in most key metrics.