Ying Xin Cui

The repetitive peak forward surge current ( I _{F , RM} ) is a practically important parameter for SiC Schottky diodes, as it ensures reliable and robust circuit designs. However, there is no established method and criterion for this imperative parameter. Manufacturers predominantly provide the non-repetitive peak forward surge current value ( I _{F , SM} ) in datasheets, which is generally determined from derated measured peak currents that cause diode failures. Consequently, it is assumed that I _F,SM enables diodes from various manufacturers with different structural designs to be compared in terms of their repetitive surge current performance. In this paper, we will demonstrate the need for a consistent criterion and a method to determine I _F,RM by analyzing repetitive surge currents in representative commercially available SiC Schottky diodes. The analysis is based on a recently proposed method and criterion for the repetitive peak surge current in SiC Schottky diodes that ensures the junction temperature does not exceed the maximum device rating, which is 175°C for the commercially available devices analysed in this study.

Silicon carbide (SiC) Schottky barrier diodes (SBDs) have become critical components in power electronics due to their excellent high-voltage, high-temperature tolerance, and fast switching capability. However, increasing device area to improve current-carrying capability increases the total number of defects, which leads to an increase in reverse leakage current and reduces wafer yield. To improve current distribution uniformity within SiC module packaging, reduce system size and weight, and enhance the current-carrying capacity and high-temperature stability of a single SBD, this paper develops 750V/100A and 1200V/100A SiC SBDs on 6-inch wafers. For the 750V/100A device, the corresponding forward voltage (V _F ) at forward current (I _F ) of 100 A is 1.68 V. For the 1200V/100A device, the corresponding V _F is 1.75V. Calculation based on the current voltage characteristics shows that the ideal factors of 750V/100A and 1200V/100A devices are 1.01 and 1.04, respectively, which are very close to 1. It demonstrates excellent Schottky contact and a high-quality interface. The devices exhibit high-temperature stability, meeting the demands of high-temperature applications.

This paper investigates the effect of DLTS measurement parameters on characterizing deep level defects in 4H-SiC Schottky barrier diode (SBD). By adjusting parameters such as the time window (t _W ), pulse time (t _P ), reverse voltage (U _R ), and pulse voltage (U _P ), the underlying mechanisms influencing defect peak positions, signal amplitudes, and peak broadening are analyzed. Experimental results reveal three deep level defects identified in 4H-SiC SBD: majority carrier traps T1 (E _C - 0.66 eV) and T2 (E _C - 1.0 eV), along with minority carrier trap T3 (E _V + 1.1 eV). Parameter settings not only influence defect characterization sensitivity and concentration calculations but also reveal the dynamics of carrier capture and emission. Through the thorough analysis of the DLTS signal and behavior under different DLTS measurement conditions, the electronic properties and concentration profiles of deep level defects in 4H-SiC epitaxial layers are determined.

High-temperature reverse bias (HTRB) is one of the most critical reliability for SiC MOSFET, and the termination region is widely regarded as the sensitive area under HTRB stress. Interestingly, through systematically monitoring of the degradation behavior of static electrical parameters under different voltage, this study reveals that the elevated reverse bias (ERB) stress can also induce damage in the gate oxide, which results in the hole trapping and a negative shift of the threshold voltage. Deep level transient spectroscopy (DLTS) measurements were performed and showed that the interface trap density in the gate oxide is promoted after ERB stress. Surprisingly, the reverse leakage current after ERB stress is significantly deteriorated at a gate bias of 0 V, while effectively suppressed by applying a negative gate bias (−5 V), which point to the synergistic effects of channel region on the breakdown voltage. Based on the gate oxide degradations and TCAD simulations, it is elucidated that the trapped positive interface charges in gate oxide cause band bending, leading to the formation of an electron accumulation layer in the channel region at 0 V gate bias and thus resulting in a dominant leakage path. This work reveals the impact and mechanism of the ERB stress induced gate oxide damage on the breakdown voltage and highlights the importance of gate oxide protection, which is of great significance for improving the reliability of SiC MOSFETs in elevated voltage applications.

In recent years, because of stringent needs in the fabrication of silicon carbide (SiC) power devices, laser annealing has been introduced to achieve local ohmic contact. In this paper, the laser annealing research for the ohmic contact process of SiC power devices is reviewed, which is mainly divided into four aspects: laser process mechanism, ohmic contact electrode materials, and substrate materials. The effect of laser parameters on ohmic contact and the annealing process on SiC diode devices is also reviewed. Progress of other substrate materials, namely 6H-SiC and semi-insulating 4H-SiC-based devices with laser annealed ohmic contacts, is also briefly discussed, in which formation of semi-insulating SiC ohmic contacts is derived from laser irradiation at the interface to produce 3C-SiC. Some experiment results have been shown in the passage, such as XRD, SEM, TEM, etc. In the review, it points out that the direction of application and development of the laser annealing process for improving the ohmic contact of SiC power devices is highly encouraging.