Chang Liu
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Research Subjects
Chang Liu has a total of 23 co-authors. Here are the top co-authors by number of shared publications:
- Dongsheng Wang
Tsinghua University
4 shared publications - Yongqiang Lyu
Tsinghua University
4 shared publications - Gang Qu
Department of Electrical and Computer Engineering & Institute for Systems Research, University of Maryland, College Park, MD, USA
3 shared publications - Pengfei Qiu
Key Laboratory of Trustworthy Distributed Computing and Service (BUPT), Ministry of Education, Beijing, Beijing, China
3 shared publications Dongsheng Wang
Department of Computer Science and Technology, Tsinghua University, Beijing, China
2 shared publications- Feng Shuaihu
Zhongguancun Laboratory, Beijing, Beijing, China
2 shared publications
Latest Publications
- 24 August 2026
- Published by Springer Nature
- p. 467-482
Pitfall: Uncovering and Exploiting the Store Forwarding Predictor on Intel CPUs
- 24 August 2026
- Published by Springer Nature
- p. 467-482
Pitfall: Uncovering and Exploiting the Store Forwarding Predictor on Intel CPUs
- Open Access
- 26 July 2026
- Published by Association for Computing Machinery (ACM)
- p. 1-7
Thrend: Mitigating Counting Thread-based Fine-grained Timing on Arm and Apple CPUs
- 26 July 2026
- Published by Association for Computing Machinery (ACM)
- p. 1-7
Open AccessThrend: Mitigating Counting Thread-based Fine-grained Timing on Arm and Apple CPUs
- 2 July 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 45 (2) , 1075-1088
Exploiting ARMeD Channels By Reverse Engineering ARM Memory Disambiguation Unit
ARM CPUs are widely used in both embedded systems and personal computers where security considerations are becoming important. Evidently, vulnerabilities on hardware components such as cache and translation look-aside buffer are well-documented. But there are much less studies on other components, especially those in the CPU backend, largely due to the unavailability of their design and implementation details. To address this gap, we present the first in-depth reverse engineering analysis of the memory disambiguation unit (MDU) in the backend of ARM CPUs. Across four microarchitectures from ARM and Apple CPUs, we identify two different MDU designs, switch-based and counter-based. We then analyze the state machine, selection mechanism, and organization of these MDU designs. We further propose new side channels and covert channels, which we call ARMeD channels, that exploit ARM MDU to leak information. We demonstrate with three attacks using ARMeD channels: 1) a cross-process covert channel; 2) website fingerprinting; and 3) a new implementation of the spectre attack. Finally, we present a defense strategy against ARMeD Channels with less than 3% degradation on the MDU’s prediction accuracy.
- 2 July 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 45 (2) , 1075-1088
Exploiting ARMeD Channels By Reverse Engineering ARM Memory Disambiguation Unit
ARM CPUs are widely used in both embedded systems and personal computers where security considerations are becoming important. Evidently, vulnerabilities on hardware components such as cache and translation look-aside buffer are well-documented. But there are much less studies on other components, especially those in the CPU backend, largely due to the unavailability of their design and implementation details. To address this gap, we present the first in-depth reverse engineering analysis of the memory disambiguation unit (MDU) in the backend of ARM CPUs. Across four microarchitectures from ARM and Apple CPUs, we identify two different MDU designs, switch-based and counter-based. We then analyze the state machine, selection mechanism, and organization of these MDU designs. We further propose new side channels and covert channels, which we call ARMeD channels, that exploit ARM MDU to leak information. We demonstrate with three attacks using ARMeD channels: 1) a cross-process covert channel; 2) website fingerprinting; and 3) a new implementation of the spectre attack. Finally, we present a defense strategy against ARMeD Channels with less than 3% degradation on the MDU’s prediction accuracy.
- Open Access
- 30 March 2025
- Published by Association for Computing Machinery (ACM)
- p. 622-638
MDPeek: Breaking Balanced Branches in SGX with Memory Disambiguation Unit Side Channels
- 30 March 2025
- Published by Association for Computing Machinery (ACM)
- p. 622-638
Open AccessMDPeek: Breaking Balanced Branches in SGX with Memory Disambiguation Unit Side Channels
- Open Access
- 23 June 2024
- Published by Association for Computing Machinery (ACM)
- p. 1-6
Whisper: Timing the Transient Execution to Leak Secrets and Break KASLR
The vulnerabilities of transient execution have been exploited in many side-channel attacks (SCA). We report Whisper, a novel transient execution timing (TET) side channel, which is based on the execution time difference of transient execution under different conditions. We develop TET version of SCAs including Meltdown, Zombieload, and Spectre-RSB that use Whisper as covert channel to leak information. We further propose TET-KASLR to break the kernel address space layout randomization (KASLR) mechanism under the protection of KPTI and FLARE. These attacks are simple to implement and can bypass the existing mitigation methods because the TET side channel relies on execution time that can be conveniently obtained by architectural level timing analysis. We demonstrate the correctness and effectiveness of these attacks on various x86-64 CPUs. The root cause of Whisper is analyzed with our toolset built on performance monitor unit (PMU) and potential defense against Whisper is also discussed.
- 23 June 2024
- Published by Association for Computing Machinery (ACM)
- p. 1-6
Open AccessWhisper: Timing the Transient Execution to Leak Secrets and Break KASLR
The vulnerabilities of transient execution have been exploited in many side-channel attacks (SCA). We report Whisper, a novel transient execution timing (TET) side channel, which is based on the execution time difference of transient execution under different conditions. We develop TET version of SCAs including Meltdown, Zombieload, and Spectre-RSB that use Whisper as covert channel to leak information. We further propose TET-KASLR to break the kernel address space layout randomization (KASLR) mechanism under the protection of KPTI and FLARE. These attacks are simple to implement and can bypass the existing mitigation methods because the TET side channel relies on execution time that can be conveniently obtained by architectural level timing analysis. We demonstrate the correctness and effectiveness of these attacks on various x86-64 CPUs. The root cause of Whisper is analyzed with our toolset built on performance monitor unit (PMU) and potential defense against Whisper is also discussed.
- 3 August 2023
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems I: Regular Papers
- Vol. 70 (12) , 5048-5059
PMU-Spill: A New Side Channel for Transient Execution Attacks
Performance Monitor Unit (PMU) is an important hardware module in mainstream processors, which counts various architectural and microarchitectural events during the run-time of the processor. Theoretically, if an instruction is executed but doesn’t successfully retire (this is called transient execution), the events it triggers needn’t be recorded by PMU. However, in this study, we discover that current PMU implementations are capable of recording some events that are triggered in transient executions, which is a hardware vulnerability. Based on this vulnerability, we propose the attack, a new kind of side channel attack that enables attackers to maliciously leak secret data in transient executions. We perform a thorough study of PMU counters on five Intel processors and find that they all have vulnerable PMU counters that will measure transient execution events (there are 162 vulnerable PMU counters among all the 383 PMU counters). We demonstrate on real hardware that 112 vulnerable PMU counters can be utilized in attack to leak the secret data protected by Intel Software Guard Extensions (SGX). Besides, our experiments suggest that the throughput of attack is up to 291.2 bytes per second (Bps) with an error rate of 2.45% on average. This discovery and the corresponding mitigation methods can be helpful for microarchitecture designers to reevaluate the security risks induced by the PMU module.
- 3 August 2023
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems I: Regular Papers
- Vol. 70 (12) , 5048-5059
PMU-Spill: A New Side Channel for Transient Execution Attacks
Performance Monitor Unit (PMU) is an important hardware module in mainstream processors, which counts various architectural and microarchitectural events during the run-time of the processor. Theoretically, if an instruction is executed but doesn’t successfully retire (this is called transient execution), the events it triggers needn’t be recorded by PMU. However, in this study, we discover that current PMU implementations are capable of recording some events that are triggered in transient executions, which is a hardware vulnerability. Based on this vulnerability, we propose the attack, a new kind of side channel attack that enables attackers to maliciously leak secret data in transient executions. We perform a thorough study of PMU counters on five Intel processors and find that they all have vulnerable PMU counters that will measure transient execution events (there are 162 vulnerable PMU counters among all the 383 PMU counters). We demonstrate on real hardware that 112 vulnerable PMU counters can be utilized in attack to leak the secret data protected by Intel Software Guard Extensions (SGX). Besides, our experiments suggest that the throughput of attack is up to 291.2 bytes per second (Bps) with an error rate of 2.45% on average. This discovery and the corresponding mitigation methods can be helpful for microarchitecture designers to reevaluate the security risks induced by the PMU module.