Yangjie Zhou
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Yangjie Zhou has a total of 70 co-authors. Here are the top co-authors by number of shared publications:
- Jingwen Leng
Shanghai Jiao Tong University, Shanghai, China
9 shared publications - Minyi Guo
Shanghai Jiao Tong University, Shanghai, China
8 shared publications - Zihan Liu
Shanghai Jiao Tong University, Shanghai, China
6 shared publications - Weihao Cui
Shanghai Jiao Tong University, Shanghai, China
5 shared publications - Cong Guo
Duke University, Durham, NC, USA
4 shared publications - Jin Song Dong
National University of Singapore, Singapore, Singapore
3 shared publications
Latest Publications
- Open Access
- 14 November 2026
- Published by Association for Computing Machinery (ACM)
- p. 1831-1846
STRIDE: Efficient Secure Transformer Inference via Inter-Operator Protocol and Operator Co-Design
- 14 November 2026
- Published by Association for Computing Machinery (ACM)
- p. 1831-1846
Open AccessSTRIDE: Efficient Secure Transformer Inference via Inter-Operator Protocol and Operator Co-Design
- Open Access
- 7 October 2026
- Published by Association for Computing Machinery (ACM)
- p. 1728-1740
AlphaCu: A Transformation-Driven Synthesis Framework for LLM-Based GPU Kernel Generation
Large language models show promise for code generation, yet their effectiveness in producing high-performance GPU kernels remains insufficiently understood. Recent agentic workflows improve over direct prompting through specialized generation roles and execution feedback, but our characterization of a representative workflow reveals failures in optimization-strategy selection, hardware-specific instruction realization, and shape-dependent parameter selection. We present AlphaCu, a transformation-driven synthesis framework for LLM-based GPU kernel generation. AlphaCu treats kernel generation as structured synthesis over explicit optimization decisions rather than end-to-end code emission. Specifically, AlphaCu represents these decisions as scoped transformation passes maintained across agent-coordinated synthesis stages, enabling compatibility checking and failure attribution. AlphaCu binds selected hardware-sensitive operations to pre-validated microkernels and uses target-device measurements to revise transformation choices and tune runtime configurations. We evaluate AlphaCu on 104 test cases covering single and fused operators across four GPU architectures: NVIDIA H100, A100, V100, and AMD MI210. Under comparable generation budgets, AlphaCu achieves 100% functional correctness on our benchmark suite and delivers an average speedup of 5.64× over prior LLM workflows, while remaining competitive with vendor libraries and tensor compilers.
- 7 October 2026
- Published by Association for Computing Machinery (ACM)
- p. 1728-1740
Open AccessAlphaCu: A Transformation-Driven Synthesis Framework for LLM-Based GPU Kernel Generation
Large language models show promise for code generation, yet their effectiveness in producing high-performance GPU kernels remains insufficiently understood. Recent agentic workflows improve over direct prompting through specialized generation roles and execution feedback, but our characterization of a representative workflow reveals failures in optimization-strategy selection, hardware-specific instruction realization, and shape-dependent parameter selection. We present AlphaCu, a transformation-driven synthesis framework for LLM-based GPU kernel generation. AlphaCu treats kernel generation as structured synthesis over explicit optimization decisions rather than end-to-end code emission. Specifically, AlphaCu represents these decisions as scoped transformation passes maintained across agent-coordinated synthesis stages, enabling compatibility checking and failure attribution. AlphaCu binds selected hardware-sensitive operations to pre-validated microkernels and uses target-device measurements to revise transformation choices and tune runtime configurations. We evaluate AlphaCu on 104 test cases covering single and fused operators across four GPU architectures: NVIDIA H100, A100, V100, and AMD MI210. Under comparable generation budgets, AlphaCu achieves 100% functional correctness on our benchmark suite and delivers an average speedup of 5.64× over prior LLM workflows, while remaining competitive with vendor libraries and tensor compilers.
- Open Access
- 26 July 2026
- Published by Association for Computing Machinery (ACM)
- p. 1-7
eLLM: Elastic Memory Management Framework for Efficient LLM Serving
- 26 July 2026
- Published by Association for Computing Machinery (ACM)
- p. 1-7
Open AccesseLLM: Elastic Memory Management Framework for Efficient LLM Serving
- Open Access
- 22 March 2026
- Published by Association for Computing Machinery (ACM)
- p. 2030-2047
Towards High-Goodput LLM Serving with Prefill-decode Multiplexing
- 22 March 2026
- Published by Association for Computing Machinery (ACM)
- p. 2030-2047
Open AccessTowards High-Goodput LLM Serving with Prefill-decode Multiplexing
- Open Access
- 15 November 2025
- Published by Association for Computing Machinery (ACM)
- p. 167-184
A Sample-Free Compilation Framework for Efficient Dynamic Tensor Computation
- 15 November 2025
- Published by Association for Computing Machinery (ACM)
- p. 167-184
Open AccessA Sample-Free Compilation Framework for Efficient Dynamic Tensor Computation
- 16 September 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 45 (5) , 2348-2361
A Full-Stack Framework for GNN Acceleration via Partition–Compiler–Architecture Co-Design
Graph neural networks (GNNs) have achieved remarkable success across domains such as recommendation and scientific computing, yet their practical deployment remains constrained by high execution cost. The diversity of GNN model structures and the sparsity of real-world graphs pose two fundamental challenges for hardware acceleration: supporting heterogeneous operator patterns and achieving high resource utilization under irregular data access. Existing accelerators often address only one aspect, either targeting specific models with hardwired pipelines or applying general architectures with limited efficiency. To address these challenges, we proposeSwitchBlade, a full-stack framework for GNN acceleration through the coordinated design of partitioning, compilation, and architecture.SwitchBlade addresses these challenges through three key components. First, a phase-based intermediate representation unifies diverse GNN models by abstracting computation stages for model-independent code generation. Second, a fine-grained graph partitioner (GP) enhances data locality and reduces memory traffic by adapting to graph topology and model semantics. Third, the hardware architecture supports stream-level parallelism and decoupled execution to exploit cross-shard and inter-phase concurrency. Evaluation on representative models and datasets shows thatSwitchBlade achieves up to$1.85\times $ speedup and$19.03\times $ energy savings over an NVIDIA V100 GPU, while outperforming state-of-the-art GNN accelerators (GAs) across diverse full-graph workloads, demonstrating both high efficiency and broad model generality.- 16 September 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 45 (5) , 2348-2361
A Full-Stack Framework for GNN Acceleration via Partition–Compiler–Architecture Co-Design
Graph neural networks (GNNs) have achieved remarkable success across domains such as recommendation and scientific computing, yet their practical deployment remains constrained by high execution cost. The diversity of GNN model structures and the sparsity of real-world graphs pose two fundamental challenges for hardware acceleration: supporting heterogeneous operator patterns and achieving high resource utilization under irregular data access. Existing accelerators often address only one aspect, either targeting specific models with hardwired pipelines or applying general architectures with limited efficiency. To address these challenges, we proposeSwitchBlade, a full-stack framework for GNN acceleration through the coordinated design of partitioning, compilation, and architecture.SwitchBlade addresses these challenges through three key components. First, a phase-based intermediate representation unifies diverse GNN models by abstracting computation stages for model-independent code generation. Second, a fine-grained graph partitioner (GP) enhances data locality and reduces memory traffic by adapting to graph topology and model semantics. Third, the hardware architecture supports stream-level parallelism and decoupled execution to exploit cross-shard and inter-phase concurrency. Evaluation on representative models and datasets shows thatSwitchBlade achieves up to$1.85\times $ speedup and$19.03\times $ energy savings over an NVIDIA V100 GPU, while outperforming state-of-the-art GNN accelerators (GAs) across diverse full-graph workloads, demonstrating both high efficiency and broad model generality.- Open Access
- 6 August 2025
- Published by Association for Computing Machinery (ACM)
- p. 247-263
Voyager: Input-Adaptive Algebraic Transformations for High-Performance Graph Neural Networks
- 6 August 2025
- Published by Association for Computing Machinery (ACM)
- p. 247-263
Open AccessVoyager: Input-Adaptive Algebraic Transformations for High-Performance Graph Neural Networks
- Open Access
- 27 April 2024
- Published by Association for Computing Machinery (ACM)
- p. 416-430
Fractal: Joint Multi-Level Sparse Pattern Tuning of Accuracy and Performance for DNN Pruning
- 27 April 2024
- Published by Association for Computing Machinery (ACM)
- p. 416-430
Open AccessFractal: Joint Multi-Level Sparse Pattern Tuning of Accuracy and Performance for DNN Pruning
- Open Access
- 9 May 2023
- Published by Association for Computing Machinery (ACM)
- p. 52-62
AdaptGear
Graph neural networks (GNNs) are powerful tools for exploring and learning from graph structures and features. As such, achieving high-performance execution for GNNs becomes crucially important. Prior works have proposed to explore the sparsity (i.e., low density) in the input graph to accelerate GNNs, which uses the full-graph-level or block-level sparsity format. We show that they fail to balance the sparsity benefit and kernel execution efficiency. In this paper, we propose a novel system, referred to as AdaptGear, that addresses the challenge of optimizing GNNs performance by leveraging kernels tailored to the density characteristics at the subgraph level. Meanwhile, we also propose a method that dynamically chooses the optimal set of kernels for a given input graph. Our evaluation shows that AdaptGear can achieve a significant performance improvement, up to 6.49× (1.87× on average), over the state-of-the-art works on two mainstream NVIDIA GPUs across various datasets.
- 9 May 2023
- Published by Association for Computing Machinery (ACM)
- p. 52-62
Open AccessAdaptGear
Graph neural networks (GNNs) are powerful tools for exploring and learning from graph structures and features. As such, achieving high-performance execution for GNNs becomes crucially important. Prior works have proposed to explore the sparsity (i.e., low density) in the input graph to accelerate GNNs, which uses the full-graph-level or block-level sparsity format. We show that they fail to balance the sparsity benefit and kernel execution efficiency. In this paper, we propose a novel system, referred to as AdaptGear, that addresses the challenge of optimizing GNNs performance by leveraging kernels tailored to the density characteristics at the subgraph level. Meanwhile, we also propose a method that dynamically chooses the optimal set of kernels for a given input graph. Our evaluation shows that AdaptGear can achieve a significant performance improvement, up to 6.49× (1.87× on average), over the state-of-the-art works on two mainstream NVIDIA GPUs across various datasets.
- Open Access
- 9 May 2023
- Published by Association for Computing Machinery (ACM)
- p. 112-122
DistSim
With the ever-increasing computational demand of DNN training workloads, distributed training has been widely adopted. A combination of data, model and pipeline parallelism strategy, called hybrid parallelism distributed training, is imported to tackle the problem of deploying large-scale models. However, how to evaluate the hybrid strategy and the utilization of each device remains a challenge since existing works either profile on a real large-scale cluster with high time and money costs or only analyze a specific type of parallelism without considering the hybrid parallelism. In this work, we proposed DistSim, an event-based performance model to accurately analyze each device's computation and communication activities with low profiling costs. DistDim breaks down the model into events according to the given distributed strategy, which can be profiled on two nodes. Then DistSim leverages the hierarchy of different parallel strategies to generate the computation and communication event-flow from layer level to model level and finally the activity timeline of each device participating in training. Experiment shows that DistSim can reach <4% errors when predicting distributing training batch time and <5% errors when predicting a single device's activity time in various hybrid strategy settings. We also provide a use-case of DistSim, automatically evaluate and search the best distributed training strategy, and find a hybrid strategy with at most 7.37× throughput improvement.
- 9 May 2023
- Published by Association for Computing Machinery (ACM)
- p. 112-122
Open AccessDistSim
With the ever-increasing computational demand of DNN training workloads, distributed training has been widely adopted. A combination of data, model and pipeline parallelism strategy, called hybrid parallelism distributed training, is imported to tackle the problem of deploying large-scale models. However, how to evaluate the hybrid strategy and the utilization of each device remains a challenge since existing works either profile on a real large-scale cluster with high time and money costs or only analyze a specific type of parallelism without considering the hybrid parallelism. In this work, we proposed DistSim, an event-based performance model to accurately analyze each device's computation and communication activities with low profiling costs. DistDim breaks down the model into events according to the given distributed strategy, which can be profiled on two nodes. Then DistSim leverages the hierarchy of different parallel strategies to generate the computation and communication event-flow from layer level to model level and finally the activity timeline of each device participating in training. Experiment shows that DistSim can reach <4% errors when predicting distributing training batch time and <5% errors when predicting a single device's activity time in various hybrid strategy settings. We also provide a use-case of DistSim, automatically evaluate and search the best distributed training strategy, and find a hybrid strategy with at most 7.37× throughput improvement.