Taiqiang Cao

To improve the tradeoff between dynamic breakdown voltage (BV_dyn) and specific on-resistance (R_on,sp) in SOI LDMOS devices, a double-step-doped SOI LDMOS with a P-type buried layer (DSD-PBL SOI LDMOS) is proposed. The device incorporates a double-step-doped (DSD) drift region and a uniformly doped P-type buried layer (PBL) beneath the buried oxide (BOX). The DSD drift region and the PBL jointly modulate the electric-field distribution, enabling a high drift-region doping concentration while preserving the breakdown capability. Simulation results show that the proposed device achieves a BV_dyn of 678 V, which is comparable to the 680 V obtained by the step-doped SOI LDMOS (SD-SOI LDMOS) with the same DSD drift region and higher than the 605 V obtained by the conventional SOI LDMOS (C-SOI LDMOS). Meanwhile, the proposed device has a R_on,sp of 7.84 Ω⋅mm², corresponding to reductions of 39.0% and 45.6% compared with the SD-SOI LDMOS and C-SOI LDMOS devices, respectively. Under identical switching and thermal-management conditions, the reduced R_on,sp results in lower conduction losses and improved thermal performance.

In this paper, the transient breakdown voltage (TrBV) of a silicon-on-insulator (SOI) laterally diffused metal-oxide-semiconductor (LDMOS) device was increased by introducing a step P-type doping buried layer (SPBL) below the buried oxide (BOX). Device simulation software MEDICI 0.13.2 was used to investigate the electrical characteristics of the new devices. When the device was turned off, the SPBL could enhance the reduced surface field (RESURF) effect and modulate the lateral electric field in the drift region to ensure that the surface electric field was evenly distributed, thus increasing the lateral breakdown voltage (BV_lat). The enhancement of the RESURF effect while maintaining a high doping concentration in the drift region (N_d) in the SPBL SOI LDMOS resulted in a reduction in the substrate doping concentration (P_sub) and an expansion of the substrate depletion layer. Therefore, the SPBL both improved the vertical breakdown voltage (BV_ver) and suppressed an increase in the specific on-resistance (R_on,sp). The results of simulations showed a 14.46% higher TrBV and a 46.25% lower R_on,sp for the SPBL SOI LDMOS compared to those of the SOI LDMOS. As the SPBL optimized the vertical electric field at the drain, the turn-off non-breakdown time (T_nonbv) of the SPBL SOI LDMOS was 65.64% longer than that of the SOI LDMOS. The SPBL SOI LDMOS also demonstrated that TrBV was 10% higher, R_on,sp was 37.74% lower, and T_nonbv was 10% longer than those of the double RESURF SOI LDMOS.