Yu Zhang
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Research Subjects
Research Interests
Yu Zhang has a total of 4 co-authors. Here are the top co-authors by number of shared publications:
- Bin Wu
The Intelligent Manufacturing Electronics R&D Center, The Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
1 shared publication - Taishan Mo
Zhejiang CASEMIC Electronics Technology Co., Ltd., Hangzhou 310051, China
1 shared publication - Tianchun Ye
The Intelligent Manufacturing Electronics R&D Center, Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China
1 shared publication - Yilin Pu
The Intelligent Manufacturing Electronics R&D Center, Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China
1 shared publication
Latest Publications
- Open Access
- 12 June 2023
- Published by MDPI AG in Applied Sciences
- Vol. 13 (12) , 7040
A 200-MS/s 10-Bit SAR ADC Applied in WLAN Systems
This paper introduces a new high-performance successive approximation register (SAR) analog-to-digital converter (ADC) designed for high-speed and low-power wireless local area network (WLAN) applications using a SMIC 55 nm 1p8m CMOS process. The design employs several innovative techniques, including an improved bootstrap switch with high linearity, a 4-reference voltage method to minimize capacitive digital-to-analog converter (CDAC) mismatch, a kickback-canceling comparator to eliminate kick-back noise, and redundant design-assisted window-opening SAR logic to decrease conversion time. Experimental results reveal that the proposed ADC achieves an impressive signal-to-noise and distortion ratio (SNDR) of 55.3 dB and a spurious-free dynamic range (SFDR) of 66.6 dB at a sampling rate of 200 MHz with Nyquist frequency input while consuming a power of 2.8 mW at a 1.2 V power supply. This corresponds to a figure-of-merit (FoM) value of 29 fJ/conversion-step. Thanks to the incorporation of the 4-reference voltage method, the ADC demonstrates a significant area advantage compared to other designs with similar FOM values utilizing more advanced processes, occupying a mere 0.008 mm2 of core area.
- 12 June 2023
- Published by MDPI AG in Applied Sciences
- Vol. 13 (12) , 7040
Open AccessA 200-MS/s 10-Bit SAR ADC Applied in WLAN Systems
This paper introduces a new high-performance successive approximation register (SAR) analog-to-digital converter (ADC) designed for high-speed and low-power wireless local area network (WLAN) applications using a SMIC 55 nm 1p8m CMOS process. The design employs several innovative techniques, including an improved bootstrap switch with high linearity, a 4-reference voltage method to minimize capacitive digital-to-analog converter (CDAC) mismatch, a kickback-canceling comparator to eliminate kick-back noise, and redundant design-assisted window-opening SAR logic to decrease conversion time. Experimental results reveal that the proposed ADC achieves an impressive signal-to-noise and distortion ratio (SNDR) of 55.3 dB and a spurious-free dynamic range (SFDR) of 66.6 dB at a sampling rate of 200 MHz with Nyquist frequency input while consuming a power of 2.8 mW at a 1.2 V power supply. This corresponds to a figure-of-merit (FoM) value of 29 fJ/conversion-step. Thanks to the incorporation of the 4-reference voltage method, the ADC demonstrates a significant area advantage compared to other designs with similar FOM values utilizing more advanced processes, occupying a mere 0.008 mm2 of core area.