Darian Reyes Fernández de Bulnes
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Research Subjects
Research Interests
Darian Reyes Fernández de Bulnes has a total of 3 co-authors. Here are the top co-authors by number of shared publications:
- Yazmin Maldonado
Tecnológico Nacional de México/IT Tijuana
2 shared publications - Juan Carlos Dibene Simental
Instituto Tecnológico de Tijuana, Tijuana, B.C., Mexico. s:
1 shared publication - Leonardo Trujillo
Instituto Tecnológico de Tijuana
1 shared publication
Latest Publications
- 1 January 2018
- Published by Instituto Politecnico Nacional/Centro de Investigacion en Computacion in Computación y Sistemas
- Vol. 22 (2) , 425-437
Comparison of Multi-objective Evolutionary Algorithms for High Level Synthesis in FPGA Devices
Operations scheduling is a fundamental problem of mapping a design into an electronic device, such as a Field Programmable Gate Array (FPGA). In this paper, a proposal for apply the multi-objective evolutionary algorithms, such as, NSGA-II, SPEA2 and NSGA-III for the simultaneous optimization of area, delay and power in the in high-level synthesis stage in the FPGAs is presented. Results obtained are compared using the quality indicators, Epsilon, Hypervolume and R, these results shown which of the algorithms are the most suitable for this problem to solve. Then, the results of the evolutionary processes are analyzed and improvements are proposed.
- 1 January 2018
- Published by Instituto Politecnico Nacional/Centro de Investigacion en Computacion in Computación y Sistemas
- Vol. 22 (2) , 425-437
Comparison of Multi-objective Evolutionary Algorithms for High Level Synthesis in FPGA Devices
Operations scheduling is a fundamental problem of mapping a design into an electronic device, such as a Field Programmable Gate Array (FPGA). In this paper, a proposal for apply the multi-objective evolutionary algorithms, such as, NSGA-II, SPEA2 and NSGA-III for the simultaneous optimization of area, delay and power in the in high-level synthesis stage in the FPGAs is presented. Results obtained are compared using the quality indicators, Epsilon, Hypervolume and R, these results shown which of the algorithms are the most suitable for this problem to solve. Then, the results of the evolutionary processes are analyzed and improvements are proposed.
- 16 May 2017
- Published by SAGE Publications in AI Communications
- Vol. 30 (2) , 151-168
High-Level Synthesis through metaheuristics and LUTs optimization in FPGA devices
Operations scheduling and Lookup Table (LUT) based technology mapping are fundamental problems of mapping designs onto an electronic device, such as a Field Programmable Gate Array. We present an approach to apply two optimizations consecutively. As
- 16 May 2017
- Published by SAGE Publications in AI Communications
- Vol. 30 (2) , 151-168
High-Level Synthesis through metaheuristics and LUTs optimization in FPGA devices
Operations scheduling and Lookup Table (LUT) based technology mapping are fundamental problems of mapping designs onto an electronic device, such as a Field Programmable Gate Array. We present an approach to apply two optimizations consecutively. As