Stefan Ivanov Stoyanov
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Research Subjects
Stefan Ivanov Stoyanov has a total of 2 co-authors. Here are the top co-authors by number of shared publications:
- Maria Marinova
Department of Computer Systems and Technologies, Faculty of Electronics and Automation, Technical University of Sofia, Branch Plovdiv, Plovdiv 4000, Bulgaria
4 shared publications - Nikolay Kakanakov
Faculty of Electronics and Automation, Plovdiv Branch, Technical University of Sofia, 4000 Plovdiv, Bulgaria
4 shared publications
Latest Publications
- Open Access
- 28 February 2026
- Published by MDPI AG in Applied Sciences
- Vol. 16 (5) , 2387
Security Interface for Execution Control from a Tightly Coupled Security Core
Preserving critical data, preventing unauthorized access, and securing communication are aspects of information security. Implementing them as hardware is more reliable than software. There are various hardware solutions that suggest using a separate computational unit, which is capable of providing various security enhancements. This article describes a heterogeneous security architecture with a tightly coupled security core to the CPU. A security interface that allows direct control and monitoring of the security core over the CPU is proposed. In the article analysis of how the interface interacts with the controlled and monitored CPU is done. This analysis explains the benefits and why for certain aspects, control is implemented seeking performance, while for others, using less logic.
- 28 February 2026
- Published by MDPI AG in Applied Sciences
- Vol. 16 (5) , 2387
Open AccessSecurity Interface for Execution Control from a Tightly Coupled Security Core
Preserving critical data, preventing unauthorized access, and securing communication are aspects of information security. Implementing them as hardware is more reliable than software. There are various hardware solutions that suggest using a separate computational unit, which is capable of providing various security enhancements. This article describes a heterogeneous security architecture with a tightly coupled security core to the CPU. A security interface that allows direct control and monitoring of the security core over the CPU is proposed. In the article analysis of how the interface interacts with the controlled and monitored CPU is done. This analysis explains the benefits and why for certain aspects, control is implemented seeking performance, while for others, using less logic.
- Open Access
- 12 February 2026
- Published by MDPI AG in Preprints.org
Security Interface for Execution Control from a Tightly-Coupled Security Core
Preserving critical data, preventing unauthorized access, securing communication are aspects of information security. To implement them as hardware is more reliable than software. There are various hardware solutions that suggest using a separate computational unit which is capable of providing various security enhancements. This article describes a heterogeneous security architecture with a tightly coupled security core to the CPU. A security interface that allows direct control and monitory of the security core over the CPU is proposed. In the article analysis of how the interface interacts with the controlled and monitored CPU is done. This analysis explains the benefits and why for certain aspects control is implemented seeking performance while for others - using less logic.
- 12 February 2026
- Published by MDPI AG in Preprints.org
Open AccessSecurity Interface for Execution Control from a Tightly-Coupled Security Core
Preserving critical data, preventing unauthorized access, securing communication are aspects of information security. To implement them as hardware is more reliable than software. There are various hardware solutions that suggest using a separate computational unit which is capable of providing various security enhancements. This article describes a heterogeneous security architecture with a tightly coupled security core to the CPU. A security interface that allows direct control and monitory of the security core over the CPU is proposed. In the article analysis of how the interface interacts with the controlled and monitored CPU is done. This analysis explains the benefits and why for certain aspects control is implemented seeking performance while for others - using less logic.
- Open Access
- 7 July 2025
- Published by MDPI AG in Engineering Proceedings
- Vol. 100 (1) , 18
FPGA Prototyping of Heterogeneous Security Architecture for Educational Purposes
Modern day hardware design is heavily focused on software simulations and verification. ASIC design is complex, and its abstraction may lead to losing motivation to develop knowledge and skills in the field. It is also very costly and inaccessible outside the industry, especially on a larger scale. FPGAs are devices which are affordable and allow unexperienced people, like students, to have an accessible and observable starting point in hardware development. On the other hand, protocol standards and devices nowadays are so complex that one will need to spend years to understand and feel comfortable dealing with corporate methodologies, environments and development process. One of the still evolving, recently developed ISA for example, RISC-V, is a broad area to learn. Often the fastest and in-depth way to learn is by observation, getting familiar with accessible yet challenging design and making modifications to and experimenting with such platforms.
- 7 July 2025
- Published by MDPI AG in Engineering Proceedings
- Vol. 100 (1) , 18
Open AccessFPGA Prototyping of Heterogeneous Security Architecture for Educational Purposes
Modern day hardware design is heavily focused on software simulations and verification. ASIC design is complex, and its abstraction may lead to losing motivation to develop knowledge and skills in the field. It is also very costly and inaccessible outside the industry, especially on a larger scale. FPGAs are devices which are affordable and allow unexperienced people, like students, to have an accessible and observable starting point in hardware development. On the other hand, protocol standards and devices nowadays are so complex that one will need to spend years to understand and feel comfortable dealing with corporate methodologies, environments and development process. One of the still evolving, recently developed ISA for example, RISC-V, is a broad area to learn. Often the fastest and in-depth way to learn is by observation, getting familiar with accessible yet challenging design and making modifications to and experimenting with such platforms.
- Open Access
- 16 June 2023
- Published by Association for Computing Machinery (ACM)
- p. 19-23
Secure Heterogeneous Architecture based on RISC-V and root-of-trust
- 16 June 2023
- Published by Association for Computing Machinery (ACM)
- p. 19-23
Open AccessSecure Heterogeneous Architecture based on RISC-V and root-of-trust