Argyro Kamperi
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Argyro Kamperi has a total of 5 co-authors. Here are the top co-authors by number of shared publications:
- Christos Dimas
School of Electrical and Computer Engineering, National Technical University of Athens, Athens, Greece
1 shared publication - Georgios Gennis
Department of Electrical and Computer Engineering, National Technical University of Athens, 15780 Athens, Greece
1 shared publication - Nikolaos P. Eleftheriou
Department of Electrical and Computer Engineering, National Technical University of Athens, 15773 Athens, Greece
1 shared publication - Paul Peter Sotiriadis
Archimedes, Athena Research Center
1 shared publication - Vassilis Alimisis
Archimedes, Athena Research Center, Marousi, Greece
1 shared publication
Latest Publications
- Open Access
- 11 October 2023
- Published by MDPI AG in Electronics
- Vol. 12 (20) , 4211
General Methodology for the Design of Bell-Shaped Analog-Hardware Classifiers
This study introduces a general methodology for the design of analog integrated bell-shaped classifiers. Each high-level architecture is composed of several Gaussian function circuits in conjunction with a Winner-Take-All circuit. Notably, each implementation is designed with modularity and scalability in mind, effectively accommodating variations in classification parameters. The operating principles of each classifier are illustrated in detail and are used in low-power, low-voltage, and fully tunable implementations targeting biomedical applications. The realization of this design methodology occurred within a 90 nm CMOS process, leveraging the Cadence IC suite for both electrical and layout design aspects. In the verification phase, post-layout simulation outcomes were meticulously compared against software-based implementations of each classifier. Through the simulation results and comparison study, the design methodology is confirmed in terms of accuracy and sensitivity.
- 11 October 2023
- Published by MDPI AG in Electronics
- Vol. 12 (20) , 4211
Open AccessGeneral Methodology for the Design of Bell-Shaped Analog-Hardware Classifiers
This study introduces a general methodology for the design of analog integrated bell-shaped classifiers. Each high-level architecture is composed of several Gaussian function circuits in conjunction with a Winner-Take-All circuit. Notably, each implementation is designed with modularity and scalability in mind, effectively accommodating variations in classification parameters. The operating principles of each classifier are illustrated in detail and are used in low-power, low-voltage, and fully tunable implementations targeting biomedical applications. The realization of this design methodology occurred within a 90 nm CMOS process, leveraging the Cadence IC suite for both electrical and layout design aspects. In the verification phase, post-layout simulation outcomes were meticulously compared against software-based implementations of each classifier. Through the simulation results and comparison study, the design methodology is confirmed in terms of accuracy and sensitivity.