Yehuda Rudin
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Research Interests
Yehuda Rudin has a total of 3 co-authors. Here are the top co-authors by number of shared publications:
- Adam Teman
EnICS Labs, Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel
1 shared publication - Yehuda Kra
Emerging Nanoscaled Integrated Circuits and Systems (EnICS) Laboratories, Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel
1 shared publication - Yonatan Shoshan
Emerging Nanoscaled Integrated Circuits and Systems (EnICS) Laboratories, Faculty of Engineering, Bar-Ilan University, Ramat Gan, Israel
1 shared publication
Latest Publications
- 23 October 2023
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems I: Regular Papers
- Vol. 71 (1) , 223-236
HAMSA-DI: A Low-Power Dual-Issue RISC-V Core Targeting Energy-Efficient Embedded Systems
The RISC-V architecture has recently emerged as a popular open source option for the design of general purpose cores with a wide spectrum of operating specifications. In this paper, we present HAMSA-DI, a small footprint, energy-efficient, embedded RISC-V core, featuring a dynamically scheduled, in-order, dual-issue processing pipeline, supporting the popular Xpulp extensions. The proposed cost-effective dual-issue implementation provides a significant performance boost and improved energy-efficiency over baseline low-power cores under common benchmarks. These include a CoreMark score of 3.48 CM/MHz ( $+$ 22%) and an Embench score of 1.3 ( $+$ 13%) with certain benchmarks displaying as much as 22% less energy than the baseline core. The proposed design was fabricated as part of a 16 nm test chip, running at 1 GHz with an 0.8V supply voltage. Silicon measurements demonstrate that the proposed core can improve performance by as much as 8for programs operating with full dual-issue utilization with energy-efficiency improving by as much as 6.5, as compared to compiled code on a single-issue core.
- 23 October 2023
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems I: Regular Papers
- Vol. 71 (1) , 223-236
HAMSA-DI: A Low-Power Dual-Issue RISC-V Core Targeting Energy-Efficient Embedded Systems
The RISC-V architecture has recently emerged as a popular open source option for the design of general purpose cores with a wide spectrum of operating specifications. In this paper, we present HAMSA-DI, a small footprint, energy-efficient, embedded RISC-V core, featuring a dynamically scheduled, in-order, dual-issue processing pipeline, supporting the popular Xpulp extensions. The proposed cost-effective dual-issue implementation provides a significant performance boost and improved energy-efficiency over baseline low-power cores under common benchmarks. These include a CoreMark score of 3.48 CM/MHz ( $+$ 22%) and an Embench score of 1.3 ( $+$ 13%) with certain benchmarks displaying as much as 22% less energy than the baseline core. The proposed design was fabricated as part of a 16 nm test chip, running at 1 GHz with an 0.8V supply voltage. Silicon measurements demonstrate that the proposed core can improve performance by as much as 8for programs operating with full dual-issue utilization with energy-efficiency improving by as much as 6.5, as compared to compiled code on a single-issue core.