Nicola Rinaldi

Experimental analysis of 4H-SiC lateral MOSFETs characteristics up to 773K is shown. The reduction of threshold voltage, V _TH , and the increase of the field effect channel mobility, µ _CH , with temperature cause an increase of MOSFET current up to 623K. However, when scattering with lattice vibration starts to be predominant, µ _CH decreases with an abrupt drop at 773K, reducing MOSFET current. Channel resistance, R _CH , decreases with the temperature up to the range between 523 K and 573 K, implying possible thermal instability effects. However, when the temperature increases over this range, the thermal scattering predominates and R _CH again increases, ensuring thermal stability of MOSFETs.

In this paper, the electrical characterizations of a 4H-SiC CMOS NOT logic gate are performed in the temperature range from 300K down to 100K and the results are analyzed. The integrated circuit is fabricated with the Fraunhofer IISB 4H-SiC 2μm CMOS technology and the lateral NMOSFET and PMOSFET have channel form factor of 6/6 and 44/6, respectively. The circuit is supplied with a 20V. The curves show a reduction of the threshold voltage from 8.96V to 6.85V reducing the temperature from 300K to 100K and an ever-widening region in the High side (NMOSFET in saturation and PMOSFET in triode regime) compared to the Low side (NMOSFET in triode and PMOSFET in saturation regime). However, the noise margins are still wide enough for practical applications, making the circuit still useful. The behavior can be ascribed to a reduction of the conductivity of the PMOSFET with the decreasing of the temperature. Finally, analysis also focuses on the power dissipation during the transition of the output voltage from high (low) to low (high).

The effects of 673K temperature anneal on a 4H-SiC CMOS NOT logic gate have been investigated. After an annealing at 673K for 30 minutes in ambient atmosphere, a shift of threshold logic voltage, V _M , towards higher input voltage by 6.67%, and a hysteresis reduction are observed. Both effects can be related to MOSFETs electrical behavior after the same thermal annealing. The threshold voltage of NMOSFET, V _{TH, N} , increases by 6.67%, whereas PMOSFET one reduces by 11.15%, allowing the V _M increase. NMOSFET shows a reduction of its trans-characteristic hysteresis, ΔV _H , by-33.3%, as well as PMOSFET one, that is by-20.4%, explaining the hysteresis reduction of NOT gate. Moreover, a more reproducible NOT transfer characteristics is obtained after the 673K annealing.

An analysis of 4H-SiC CMOSFETs electrical characteristics is reported up to a temperature of 773 K taking into account the effects of the channel lengths, i.e., 2 and ${6}~\mu \text {m}$ , and of the physical parameters. Even though the threshold voltage and the channel mobility have similar dependencies on the geometry and temperature, they are described by quite different phenomena. For NMOSFET, the threshold voltage has a further reduction with the channel shortening and with the temperature due to 4H-SiC/SiO₂ interface defects, instead its maximum channel mobility of around ${21}.{75}~\text {cm}^{{2}}/\text {V}/\text {s}$ results almost the same up to 723K but then drastically reduces to ${14}.{28}~\text {cm}^{{2}}/\text {V}/\text {s}$ due to lattice vibration scattering. On the other hand, PMOSFET shows a hump of the threshold voltage with the reduction of the channel length, ascribing to a reverse short-channel effect, whereas the channel mobility is strongly affected by p-type parasitic series resistances. Due to the concomitant effects of the threshold voltage and of the channel mobility, the current increases with the temperature up to the range of [523–623] K, depending on the channel size, but then decreases, avoiding the thermal run-away effect.

A 4H-Silicon Carbide (4H-SiC) complementary to absolute temperature sensor is characterized and analyzed in the operating temperature range between 14 K and 481 K and is based on 4H-SiC diode-connected lateral NMOSFET. It is an integrated circuit compatible with 4H-SiC CMOS technology. The sensor characteristic has a unique linear curve from 481 K down to 150 K, for saturation, or to 100 K, for subthreshold bias regime. In both cases, the linearity is high, with a coefficient of determination, $R^{2}>0.99$, and the sensitivity varies from $-$ 1.98 to $-$ 7.7 mV/K. The analysis shows that the limitation of the single transistor T-sensor, due to the oxide/semiconductor interface traps, is overcome by applying two different bias currents, whereas at very low temperatures, the loss of linearity is due to the increase of the effective channel mobility (saturation) or to the increase of the slope of the single transcharacteristics (subthreshold).

In this article, we propose a postprocessing annealing for 4H-silicon carbide (SiC) CMOS technology with the aim of improving the electrical characteristics of the single devices and ICs in terms of uniformity among different dies and repeatability after thermal stress. The postprocessing annealing is performed at 673 K and under different environmental conditions, i.e., ambient, vacuum, and nitrogen, whereas the electrical characteristics are measured for 4H-SiC lateral n-type and p-type metal oxide semiconductor field-effect transistors and for integrated logic gates up to 673 K and after different thermal ramps. All the postprocessing annealing conditions induce a variation in the threshold voltages for both MOSFETs, whereas the field-effect channel mobilities result almost unchanged. For example, the threshold voltage of NMOSFETs increases, reducing the current by $-{9}.{1}\%$ , and that of PMOSFETs decreases with a rise of the current of ${25}\%$ , together with a reduction of the hysteresis of subthreshold characteristics, whereas the field-effect channel mobilities are unchanged. Furthermore, 4H-SiC CMOS not logic gates have a shift of the logical threshold toward higher values, very close to the ideal value and a better repeatability of transfer characteristics from room temperature up to 673 K. In a first analysis supported by theoretical models, we can ascribe the effects of the postprocessing annealing to a reduction of the concentration of border traps located in the oxide, which significantly affect the threshold voltage and the subthreshold characteristics, but barely alter the field-effect channel mobility.

This study investigates a tungsten oxide functionalized with platinum nanoparticles and graphene as a chemiresistive material for hydrogen gas sensing. The sensor exhibits a linear DC response ranging from 10 ppm to 25000 ppm hydrogen with a 10 ppm detection limit for an operating temperature of 200°C and for a 50% relative humidity. Furthermore, AC measurements at various frequencies reveal a reduction in sensitivity at higher frequencies, accompanied by an improved baseline, leading to more reproducible measurements. Admittance spectroscopy provides an RC equivalent circuit model, offering insights into the sensor’s interaction mechanism with hydrogen gas. A sensing mechanism is proposed and involves the adsorption of hydrogen molecules onto Pt nanoparticles, followed by dissociation and spillover of hydrogen species onto the tungsten oxide surface.

A temperature sensor based on a diode-connected 4H-Silicon Carbide p-type metal oxide semiconductor field effect transistor is characterized in the temperature range between 14K and 482K and its performance has been analysed. The study shows that the sensor characteristics are mainly affected by the threshold voltage, but an unusual reduction of the device current is shown for temperatures lower than 76K, which limits the linearity of the sensor response. Indeed, two operating temperature ranges could be defined. The first one is in the range 76K ≤ T ≤ 175K, showing a linearity of 0.991 in terms of coefficient of determination and a sensitivity of 6.24mK/K at a device current of 3.34nA, instead the second range is for temperatures higher than 175K with a linearity of 0.986 and a sensitivity of 66.37mV/K for a current of 263nA. Moreover, the device is fully compatible with 4H-SiC CMOS technology making possible its use in integrated circuits.