Yang Qiu

Integrating barium titanate (BTO) films on SiO2/Si-based platforms is essential for the development of future nanophotonic modulators in photonic integrated circuits (PIC). However, the integration of BTO films on these amorphous platforms is far from trivial. In this work, the direct growth of tetragonal crystal (p4 mm)-textured BTO films on 4-in. SiO2/Si using a magnesium oxide (MgO) buffer layer by a magnetron sputtering process is developed. This work presents a systematic study on the evolution of crystallographic orientation and anisotropy energy in BTO films as a function of film thickness. Furthermore, a detailed analysis is conducted on the growth kinetics of BTO films, with the thickness-dependent evolution of surface morphology and Ba/Ti. Simultaneously, strain-engineered BTO films with a Curie temperature (Tc > 360 °C) are demonstrated. This integration method overcomes the lattice matching limitation between BTO and the amorphous substrate, offering a low-cost, flexible integration approach for next-generation PIC platforms.

Optical through silicon vias (OTSVs) have been regarded as a promising alternative to conventional (electrical) through silicon vias (TSVs) for the next-generation electro-optic heterogeneous integration. This study systematically examines the influence of fabrication imperfections on the transmission performance in terms of incident light misalignment, via geometry variation, and sidewall roughness. The results demonstrate that over a finite range of beam widths, the insertion loss can be maintained at a relatively low level of less than −0.16 dBm, and this low-loss window broadens with increasing via diameter. Moreover, an increased diameter exhibits greater tolerance to the lateral offset, as for 10 μm, 20 μm, and 30 μm vias, the insertion loss rises to 3 dB at axis misalignments of 5 μm, 10 μm, and 15 μm, respectively. Additionally, smaller-diameter OTSVs are considerably more sensitive to sidewall slope angles than their larger-diameter counterparts. Additionally, minimizing the sidewall roughness is critical for maximizing the coupling efficiency, which suggests that the etch-passivation shift needs to be as quick as possible during the deep reactive ion etch (DRIE) process. With the proposed fabrication approach and comprehensive analysis of fabrication imperfection factors, this study provides essential insights for the development of high-performance OTSVs in advanced 3D optoelectronic integration.

Glass interposers comprising vertical through glass vias (TGVs) and horizontal redistribution layers (RDLs) have been recognized as a promising platform for heterogeneous integration. This letter presents a unique RDL-free glass interposer with simplified manufacturing process and enhanced interfacial reliability by replacing the RDLs with shallow surface trenches. All trenches and TGVs are formed through standard laser-induced wet etching (LIWE) and metallized by vacuum assisted suction of Ag nanoparticle filled polymer (ANFP) simultaneously. Experimental outcomes demonstrate that an interconnected TGV (50 μm in diameter, 500 μm in height) and trench (50 μm in cross-sectional sidelength, 2500 μm in length) can be completely filled within only 5 s. Preliminary daisy-chain measurements suggest an average resistance lower than 90 mΩ at 23 °C for these unified microchannels. Thermal characterization indicates acceptable electrical performance and reliability. By eliminating Cu electroplating and mitigating the risk of RDL delamination, the proposed RDL-free glass interposer offers a promising solution for heterogeneous integration.

Cryogenic photodetectors with ultra-low static power and high bandwidth are critical for cryogenic-to-room-temperature optical interconnects—a key solution for addressing the stringent thermal budgets of superconducting quantum computing systems, where available cooling power is severely constrained. In this Letter, we demonstrate a CMOS-compatible lateralgermanium-on-silicon (Ge-on-Si) p-i-nphotodetector. At 11 K and a reverse bias of −0.1 V, the device achieves a 3-dB bandwidth exceeding 50 GHz and a near-infrared responsivity of 0.60 A/W. Notably, the static dark power is limited to only 2 pW.Systematic electrical and optoelectronic characterization from 300 to 11 K further establishes the basis for stable low-bias cryogenic operation and shows that, upon cooling, the dark current is strongly suppressed while the high-frequency response is enhanced across the measured temperature range.These results demonstrate the potential of Ge-on-Si photodetectors to provide simultaneous high-speed operation and picowatt-level static darkpower consumption for scalable cryogenic optical data links.

Cu electroplating is one of the most expensive, complex and critical steps in fabricating through-glass vias (TGVs), which serve as the core component of 2.5D or 3D integration. This paper presents a simplified 2D via electroplating model to systematically investigate the influences of electrolyte additive, current density, and via geometry on plating performance in terms of via filling profile and Cu thickness. Under a fixed accelerator concentration of 0.1 mol/m³, plating performance for both blind- and through-vias initially improves but subsequently deteriorates with increasing suppressor concentration. Notably, the through-via filling mode dramatically transitions from super-conformal to sub-conformal, achieving a maximum throwing power (TP) of 135.74%. A gradual growth in current density from 0.1 to 0.3 amps/dm² (ASD) leads to deteriorating plating quality for both via types, with the through-via TP dropping to 95.56%. In addition, sub-conformal filling occurs in U-shaped, V-shaped, and X-shaped blind-vias if single-sided plating is employed. However, after shifting them to a through configuration with double-sided plating, complete filling can be realized across all cases. These findings offer a theoretical foundation and practical guidance for enhancing the depositing rate and minimizing/eliminating internal void for the Cu electroplating of TGVs.

Barium titanate (BaTiO3, BTO) is a promising material for integrated photonics, but surface roughness introduced during thin-film growth degrades optical performance. An argon (Ar) ion-beam polishing process is developed for BTO thin films. The effects of ion energy, beam current, incidence angle, and removed thickness on surface morphology evolution are systematically examined. An incidence-angle response function is used to describe the angular dependence of the morphology evolution. At near-normal incidence (0° to −30°), grain-induced surface undulations are suppressed by ion-induced surface-parallel atomic redistribution, which promotes surface smoothing. An effective polishing window is identified at 300 eV, 100 mA, and 0° to −30°. Under these conditions, the root mean square roughness is reduced from 5.69 to 1.34 nm, corresponding to a 76.5% reduction. In addition, post-polishing annealing at 600 °C in oxygen helps relieve Ar-induced compressive stress and facilitates recrystallization in the near-surface damaged region. These results provide a practical polishing–annealing route toward the integration of high-quality BTO thin films into low-loss photonic devices.