Marcin Aftowicz
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Research Subjects
Marcin Aftowicz has a total of 7 co-authors. Here are the top co-authors by number of shared publications:
- Ievgen Kabin
IHP—Leibniz-Institut für innovative Mikroelektronik, 15236 Frankfurt (Oder), Germany
4 shared publications - Zoya Dyka
IHP—Leibniz-Institut für innovative Mikroelektronik, 15236 Frankfurt (Oder), Germany
3 shared publications - Peter Langendoerfer
Department of Wireless Systems, BTU Cottbus-Senftenburg, Cottbus, Germany, Germany
2 shared publications - Dan Klann
IHP—Leibniz-Institut für innovative Mikroelektronik, 15236 Frankfurt (Oder), Germany
1 shared publication Peter Langendoerfer
1 shared publicationPeter Langendörfer
Leibniz-Institut fur innovative Mikroelektronik - IHP,Frankfurt (Oder),Germany
1 shared publication
Latest Publications
- Open Access
- 29 January 2024
- Published by MDPI AG in Future Internet
- Vol. 16 (2) , 45
Non-Profiled Unsupervised Horizontal Iterative Attack against Hardware Elliptic Curve Scalar Multiplication Using Machine Learning
While IoT technology makes industries, cities, and homes smarter, it also opens the door to security risks. With the right equipment and physical access to the devices, the attacker can leverage side-channel information, like timing, power consumption, or electromagnetic emanation, to compromise cryptographic operations and extract the secret key. This work presents a side channel analysis of a cryptographic hardware accelerator for the Elliptic Curve Scalar Multiplication operation, implemented in a Field-Programmable Gate Array and as an Application-Specific Integrated Circuit. The presented framework consists of initial key extraction using a state-of-the-art statistical horizontal attack and is followed by regularized Artificial Neural Networks, which take, as input, the partially incorrect key guesses from the horizontal attack and correct them iteratively. The initial correctness of the horizontal attack, measured as the fraction of correctly extracted bits of the secret key, was improved from 75% to 98% by applying the iterative learning.
- 29 January 2024
- Published by MDPI AG in Future Internet
- Vol. 16 (2) , 45
Open AccessNon-Profiled Unsupervised Horizontal Iterative Attack against Hardware Elliptic Curve Scalar Multiplication Using Machine Learning
While IoT technology makes industries, cities, and homes smarter, it also opens the door to security risks. With the right equipment and physical access to the devices, the attacker can leverage side-channel information, like timing, power consumption, or electromagnetic emanation, to compromise cryptographic operations and extract the secret key. This work presents a side channel analysis of a cryptographic hardware accelerator for the Elliptic Curve Scalar Multiplication operation, implemented in a Field-Programmable Gate Array and as an Application-Specific Integrated Circuit. The presented framework consists of initial key extraction using a state-of-the-art statistical horizontal attack and is followed by regularized Artificial Neural Networks, which take, as input, the partially incorrect key guesses from the horizontal attack and correct them iteratively. The initial correctness of the horizontal attack, measured as the fraction of correctly extracted bits of the secret key, was improved from 75% to 98% by applying the iterative learning.
- 28 December 2023
- Published by Elsevier in Microprocessors and Microsystems
- Vol. 105
Advantages of unsupervised learning analysis methods in single-trace SCA attacks
- 28 December 2023
- Published by Elsevier in Microprocessors and Microsystems
- Vol. 105
Advantages of unsupervised learning analysis methods in single-trace SCA attacks
- 6 September 2023
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 708-713
Non-Profiled Semi-Supervised Horizontal Attack Against Elliptic Curve Scalar Multiplication Using Support Vector Machines
There are different ways to leverage Side Channel information into a successful attack against cryptographic hardware. The most constraint attack scenario assumes no knowledge about the internal states of the hardware during secret key processing and therefore provides no labels for power hungry deep learning algorithms, which are the state of the art in profiling attacks. In our non-profiled single-trace attack we used a statistical method the comparison to the mean to retrieve the initial key candidates and trained a highly regularized Support Vector Machine (SVM) using those candidates. We achieved an improvement in attack correctness of about 10 % between the initial and final key candidates. We attacked two implementations of Elliptic Curve Scalar Multiplication. One is an ASIC produced in the IHP 250nm technology, where the hardware description was compiled using the compile_ultra option, which has been proven to increase the resistance against SCA attacks. Another one is an FPGA implementation, using the sequential addressing countermeasure, which minimizes the number of clock cycles with bus addressing leakage.
- 6 September 2023
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 708-713
Non-Profiled Semi-Supervised Horizontal Attack Against Elliptic Curve Scalar Multiplication Using Support Vector Machines
There are different ways to leverage Side Channel information into a successful attack against cryptographic hardware. The most constraint attack scenario assumes no knowledge about the internal states of the hardware during secret key processing and therefore provides no labels for power hungry deep learning algorithms, which are the state of the art in profiling attacks. In our non-profiled single-trace attack we used a statistical method the comparison to the mean to retrieve the initial key candidates and trained a highly regularized Support Vector Machine (SVM) using those candidates. We achieved an improvement in attack correctness of about 10 % between the initial and final key candidates. We attacked two implementations of Elliptic Curve Scalar Multiplication. One is an ASIC produced in the IHP 250nm technology, where the hardware description was compiled using the compile_ultra option, which has been proven to increase the resistance against SCA attacks. Another one is an FPGA implementation, using the sequential addressing countermeasure, which minimizes the number of clock cycles with bus addressing leakage.
- Open Access
- 30 June 2021
- Published by Springer Nature in Journal of Electronic Testing
- Vol. 37 (3) , 289-303
Resistance of the Montgomery Ladder Against Simple SCA: Theory and Practice
The Montgomery kP algorithm i.e. the Montgomery ladder is reported in literature as resistant against simple SCA due to the fact that the processing of each key bit value of the scalar k is done using the same sequence of operations. We implemented the Montgomery kP algorithm using Lopez-Dahab projective coordinates for the NIST elliptic curve B-233. We instantiated the same VHDL code for a wide range of clock frequencies for the same target FPGA and using the same compiler options. We measured electromagnetic traces of the kP executions using the same input data, i.e. scalar k and elliptic curve point P, and measurement setup. Additionally, we synthesized the same VHDL code for two IHP CMOS technologies, for a broad spectrum of frequencies. We simulated the power consumption of each synthesized design during an execution of the kP operation, always using the same scalar k and elliptic curve point P as inputs. Our experiments clearly show that the success of simple electromagnetic analysis attacks against FPGA implementations as well as the one of simple power analysis attacks against synthesized ASIC designs depends on the target frequency for which the design was implemented and at which it is executed significantly. In our experiments the scalar k was successfully revealed via simple visual inspection of the electromagnetic traces of the FPGA for frequencies from 40 to 100 MHz when standard compile options were used as well as from 50 MHz up to 240 MHz when performance optimizing compile options were used. We obtained similar results attacking the power traces simulated for the ASIC. Despite the significant differences of the here investigated technologies the designs’ resistance against the attacks performed is similar: only a few points in the traces represent strong leakage sources allowing to reveal the key at very low and very high frequencies. For the “middle” frequencies the number of points which allow to successfully reveal the key increases when increasing the frequency.
- 30 June 2021
- Published by Springer Nature in Journal of Electronic Testing
- Vol. 37 (3) , 289-303
Open AccessResistance of the Montgomery Ladder Against Simple SCA: Theory and Practice
The Montgomery kP algorithm i.e. the Montgomery ladder is reported in literature as resistant against simple SCA due to the fact that the processing of each key bit value of the scalar k is done using the same sequence of operations. We implemented the Montgomery kP algorithm using Lopez-Dahab projective coordinates for the NIST elliptic curve B-233. We instantiated the same VHDL code for a wide range of clock frequencies for the same target FPGA and using the same compiler options. We measured electromagnetic traces of the kP executions using the same input data, i.e. scalar k and elliptic curve point P, and measurement setup. Additionally, we synthesized the same VHDL code for two IHP CMOS technologies, for a broad spectrum of frequencies. We simulated the power consumption of each synthesized design during an execution of the kP operation, always using the same scalar k and elliptic curve point P as inputs. Our experiments clearly show that the success of simple electromagnetic analysis attacks against FPGA implementations as well as the one of simple power analysis attacks against synthesized ASIC designs depends on the target frequency for which the design was implemented and at which it is executed significantly. In our experiments the scalar k was successfully revealed via simple visual inspection of the electromagnetic traces of the FPGA for frequencies from 40 to 100 MHz when standard compile options were used as well as from 50 MHz up to 240 MHz when performance optimizing compile options were used. We obtained similar results attacking the power traces simulated for the ASIC. Despite the significant differences of the here investigated technologies the designs’ resistance against the attacks performed is similar: only a few points in the traces represent strong leakage sources allowing to reveal the key at very low and very high frequencies. For the “middle” frequencies the number of points which allow to successfully reveal the key increases when increasing the frequency.