Pooja Srivastava

This work compares FinFET, JLFET, and nanosheet FETs with III–V channel materials at different temperatures. Using Silvaco TCAD simulations, the threshold voltage, carrier mobility, ON/OFF current ratio, and subthreshold swing evolution with temperature are examined, and their effects on reliability are investigated. Nanotransistors offer several advantages, including compact size, rapid switching speed, and low power consumption; however, they also present practical issues, such as fabrication complexity, heat management, and thermal sensitivity. This paper helps find the best nanotransistor design for future technologies by clearly integrating temperature dependency with material choice and device architecture. These findings are useful for AI accelerators, 5G communication networks, and portable electronics, which need efficient and thermally stable equipment. Traditional planar MOSFETs face short-channel effects, increased leakage currents, and reduced reliability as CMOS technology scales into the nanometer range. FinFETs, Junctionless FETs, and Gate-All-Around (GAA) Nanosheet FETs enhance electrostatic control and efficiency, thereby overcoming these challenges. Due to their high electron mobility and outstanding transport properties, III–V compound semiconductors such as GaAs, InGaAs, and InP are promising candidates for next-generation high-speed, low-power devices. Most studies have focused on device scaling or material properties, but the effect of temperature variation on III–V nanotransistors across different topologies has not been extensively studied.

The continued miniaturization of transistors has led to modern electronics, but traditional silicon-based devices are facing severe challenges, particularly in extreme environments such as space. The severe space conditions, radiation, extreme temperature changes, and vacuum require devices that are more rugged and have higher performance. In this work, the performance of nano-transistors, specifically Junctionless Field-Effect Transistors (JLFETs), Fin Field-Effect Transistors (FinFETs), and Nanosheets using new III-V semiconductor materials, has been studied. Short-channel effects (SCEs) such as drain-induced barrier lowering (DIBL) and subthreshold swing (SS) become increasingly important as transistors are scaled down, degrading performance and increasing power consumption. Nano-transistors are prospective architectures that offer better gate control over the channel, essentially preventing these SCEs from happening as opposed to conventional planar transistors. Additionally, material substitution through the exploitation of III-V materials, such as Indium Gallium Arsenide (InGaAs) and Gallium Arsenide (GaAs), has the potential to increase operating speeds and reduce power, which are critical values in space-based systems. A comparative study has been conducted between the electrical characteristics of JLFETs and FinFETs using III-V materials, including on-current, off-current, and the ION/IOFF ratio. Their resistance to the stresses of individual space environments, including radiation damage and temperature cycling, is also considered in this work. The purpose of this work is to provide a comparative foundation for selecting the most desirable nano-transistor structure and material combination for future space applications, where maximum performance and reliability are the primary factors.

With the advancement of the semiconductor industry into the sub-10 nm regime, high-performance, low-energy transistors have become important, and gate-all-around junctionless field-effect transistors (GAA-JLFETs) have been developed to meet the demands. Silicon (Si) is still the dominant semiconductor material, but other potential alternatives, such as gallium arsenide (GaAs), provide much higher electron mobility, improving the drive current and switching speed. In this study, our contributions include a comparative analysis of Si and GaAs-based cylindrical GAA-JLFETs, using threshold voltage behavior, electrostatic control, short channel effects, subthreshold slope, drain-induced barrier lowering, and leakage current as the metrics for performance evaluation. A comprehensive analytical modeling approach is employed, solving Poisson’s equation and utilizing numerical simulations to assess device characteristics using the ATLAS SILVACO tool under varying channel lengths and gate biases. Comparisons between Si and GaAs-based devices show what trade-offs exist and what the material engineering strategies are to use the advantages of GaAs while minimizing some disadvantages. The results of the study are a valuable contribution to the design and optimization of next-generation FET architectures, pointing the direction for enabling next-generation beyond CMOS technology.

In this work, a cylindrical gate-all-around junctionless field effect transistor (JLFET) was investigated. Junctions and doping concentration gradients are unavailable in JLFET. According to the results, the suggested device has a novel architecture that significantly enhances transistor performance while exhibiting a decreased vulnerability to short-channel effects (SCEs). The Atlas 3D device simulator has been used to analyze the proposed JLFET’s performance, especially for low-power applications for different channel lengths ranging from 10 nm to 60 nm with Al_0.30Ga_0.60As as III-V materials. The comparative simulated study has been based on various performance parameters, including subthreshold slope (SS), drain-induced barrier lowering (DIBL), transconductance, threshold voltage, and I_ON to I_OFF ratio. The results of the simulations demonstrated that the III-V JLFET exhibited a favorable SS and decreased DIBL compared to other circuit topologies. In the suggested study, gallium arsenide (GaAs) and its compound materials have demonstrated a strong correlation between the SS and DIBL values. The SS is approximately 63 mV/dec, extremely near the ideal 60 mV/dec value. Gallium arsenide (GaAs) and aluminum gallium arsenide (AlGaAs) exhibit DIBL of approximately 30 mV/V and an SS value of around 64 mV/dec.

With the advancement of the semiconductor industry into the sub-10 nm regime, high-performance, low-energy transistors have become important, and gate-all-around junctionless field-effect transistors (GAA-JLFETs) have been developed to meet the demands. Silicon (Si) is still the dominant semiconductor material, but other potential alternatives like gallium arsenide (GaAs) provide much higher electron mobility, improving the drive current and switching speed. In this study, our contributions are a comparative analysis of Si and GaAs-based cylindrical GAA-JLFETs, using threshold voltage behavior, electrostatic control, short channel effects, subthreshold slope, drain-induced barrier lowering, and leakage current as the metrics in the evaluation of performance. A comprehensive analytical modeling approach is employed, solving Poisson's equation and utilizing numerical simulations to assess device characteristics using the ATLAS SILVACO tool under varying channel lengths and gate biases. Comparisons between Si and GaAs-based devices show what trade-offs exist and what the material engineering strategies are to use the advantages of GaAs and reduce some disadvantages. The results from the study are a valuable contribution to the design and optimization of next-generation FET architectures, pointing the direction for enabling next-generation beyond CMOS technology.

In this work, a cylindrical gate-all-around junctionless field effect transistor (JLFET) has been investigated. Junctions and doping concentration gradients are unavailable in JLFET. According to the results, the suggested device has a novel architecture that significantly enhances transistor performance while exhibiting a decreased vulnerability to short-channel effects (SCEs). The Atlas 3D device simulator has been used to analyze the proposed JLFET's performance, especially for low-power applications for different channel lengths ranging from 10 nm to 60 nm with Al0.30Ga0.60As as III-V materials. The comparative simulated study has been based on various performance parameters, including subthreshold slope (SS), drain-induced barrier lowering (DIBL), transconductance, threshold voltage, and ION to IOFF ratio. The results of the simulations demonstrated that the III-V JLFET exhibited a favorable subthreshold slope and decreased DIBL compared to other circuit topologies. In the suggested study, gallium arsenide (GaAs) and its compound materials have demonstrated a strong correlation between the SS and DIBL values. The SS is approximately 63 mV/V, extremely near the ideal 60 mV/V value. Gallium arsenide (GaAs) and aluminum gallium arsenide (AlGaAs) exhibit DIBL of approximately 30 mV/dec and a subthreshold value of around 64 mV/V.

The advent of device miniaturization techniques and the evolution of very deep submicron technology have led to the increased prominence of short channel effects (SCEs) in conventional transistors (CTs). Now, in the era of nanoengineering and nano-wires, current research is centered around a novel device known as the Junctionless Field Effect Transistor (JLFET), which incorporates gate-all-around engineering applications. Given the challenges associated with scaling transistor sizes, such as creating high-quality junctions and changing doping concentrations (~1019 cm–3) over a 10 nm distance, JLFET emerges as a promising alternative to CTs. Notably, JLFET lacks junctions and doping concentration gradients. In this study, the authors have conducted a comprehensive analysis and performance evaluation of JLFET and CTs, specifically in the context of low-power applications. Various performance parameters of JLFET, including SS, DIBL, transconductance, output conductance, and Ion/Ioff, have been assessed. The findings indicate that JLFET exhibits reduced susceptibility to SCEs compared to CTs and demonstrates exceptional current driving capability.