Xufan Li

Realising ubiquitous environmental monitoring and smart sensing devices compatible with Internet of Things (IoT) and 6 G networks requires transistors with terahertz (THz) cutoff frequencies (f_T) for efficient signal processing. However, the carrier transit time intrinsically limits conventional devices. Vertical two-dimensional (2D) base transistors offer a way to exceed this limit, yet interface losses typically suppress current gain, degrade high-frequency performance, and hinder THz operation. Here, we report a silicon–graphene–germanium barristor that overcomes these obstacles. Wafer-scale single-crystal graphene was epitaxially grown on germanium and integrated with silicon membranes, forming asymmetric Schottky barriers at the graphene–silicon and graphene–germanium interfaces. Using graphene’s quantum capacitance, the asymmetric barriers enable distinct hot-carrier emission at both terminals and greatly increase the current gain, while graphene’s atomic thickness minimises the perpendicular transit time. As a result, the device achieves a current gain up to 1.8 × 10⁷ and an intrinsic f_T up to 132 GHz, with modelling and simulation indicating scalability into the THz regime. These findings establish a promising high-frequency transistor paradigm for IoT sensors and systems.

For high-density 3D DRAM, the voltage drops of Through-Silicon-Via are nonnegligible among stacks of layers, requiring high-gain sense amplifier (SA) design. Considering back-end of line (BEOL) compatibility, independent dual-gate (IDG) IGZO FETs are promising not only for multi-bit DRAM design but also for applications in SA input transistors. This letter investigates the important analog figures of merit (FOMs) of DG IGZO FETs under various operating conditions. TCAD simulations validated by experimental data reveal that top-gate misalignment (ranging from 25% to 100%) exhibits electric field distribution variations. The trade-off between transconductance generation factor and intrinsic gain is obviously observed. Such a top-gate misalignment effect causes threshold voltage shifts and circuit mismatches in DRAM SAs, and the mismatch can be compensated by independent top-gate biasing, enabling threshold voltage modulation. IDG IGZO FETs indicate superior gain performance compared to single-gate IGZO FETs and lower leakage current than Si-based FETs, which are critical for SA input transistors. These findings provide important guidance for optimizing dual-gate IGZO FETs in analog applications, particularly for BEOL-memory SAs that need both high gain and fast response speed.

Artificial sense technologies predominantly rely on visual and tactile input, which often prove inadequate in obscured or opaque environments. Inspired by the natural electrosensory capabilities of electrogenic fishes, we introduce an organic electrosense transistor designed to detect electric fields generated by nearby objects, facilitating the creation of impalpable perception systems. Unlike traditional sensors, our electrosense transistor perceives bipolar electric fields with high sensitivity and stability. We use compact models and device simulations to elucidate the mechanisms of charge induction and transport within organic electrosense transistors when exposed to spatial electric fields. Demonstrating its practical utility, we show that robots equipped with our electrosense transistor can successfully navigate and detect concealed objects without requiring direct contact. This work not only advances the understanding of charge dynamics in electrosensory systems but also establishes a platform for developing highly sensitive, noninvasive artificial sensing technologies applicable in surveillance, search and rescue, and other challenging environments.

Gate oxide reliability has become a significant concern for emerging technology nodes, particularly as transistors continue to scale down. Quantum confinement effects in nano-scaled devices complicate the trapping dynamics near the interface. Although these behaviors can be modeled using density-functional theory (DFT) and Marcus theory, a more efficient method is essential for characterizing critical reliability issues at the nano-device level. This paper presents a pioneering numerical study that employs a Bohm potential and Marcus theory, examining carrier concentration decay near the channel/oxide interface to evaluate the charge-trapping process using density-gradient coupled Poisson equations. This approach incorporates vital quantum corrections to classical studies. Key physics-based parameters are initially derived from DFT calculations and subsequently calibrated against experimental data. Our findings indicate that charge trap rates decrease with carrier density at the interface, ultimately affecting the device's threshold voltage shift.

The designability of organic semiconductors (OSCs) enables the tunable properties of organic field-effect transistors (OFETs) with significant potential applications in flexible displays, wearable devices, and bioelectronic devices. The introduction of alkyl chains has been proved to effectively modulate the mobility, crystallinity, solubility, and other optoelectronic properties of OSCs. Here, we revealed that the alkyl chains can function as dielectric components in OFETs due to their insulating effect. The ultrathin alkyl chains are covalently bonded to the OSC backbone, eliminating the heterogeneous charge transport interface and reducing the trap density, which enables low-power and high-stability alkylated-OFETs. The 2,9-didecyldinaphtho[2,3-b:2’,3’-f]thieno[3,2-b]thiophene (C10-DNTT) FET with alkyl chain exhibits a mobility of 11.6 cm2 V−1 s−1 and an ultrahigh intrinsic gain of 7.52×104 at operational voltage of 1 V. The corresponding inverters show exceptional static (small-signal gains of 127.6 and total noise margin of 95.3% at VDD = 2.5 V) and dynamic characteristics (signal-delay time constants of 50 μs at VDD = 1 V) under low voltage. Additionally, the C10-DNTT FETs and inverters demonstrate outstanding operational stability, enduring 30000 seconds of bias stress and cycle tests. This work offers a solution for achieving both low-power and high-stability organic electronic and optoelectronic application.

Time-delayed reservoir computing (RC) equipped with prominent superiorities such as easy training and friendly hardware implementation is identified as a high-efficient answer to complex temporal tasks, and thereby draws increasing attention. Oxygen ion-based oxide electrolyte-gated transistor (Ox-EGT) with rich ion dynamic characteristics is deemed as a promising candidate for RC. However, it is still a challenge to produce the required dynamic characteristics for RC implementation. Herein, we develop an Ox-EGT with an oxygen vacancy-electron-coupled electric-double-layer at the electrolyte/channel interface to implement time-delayed RC. Effects of oxygen vacancy concentration on the short-term plasticity are investigated, revealing the optimal concentration range of oxygen vacancies for the dynamic characteristics improvement. The underlying physical mechanism is demonstrated by TCAD simulations. Simulations using the waveform classification and handwritten-digit recognition tasks validate the good information processing ability of the Ox-EGT RC system. These results provide a promising approach to exploit Ox-EGT dynamics for large-scale and energy-efficient neuromorphic computing hardware.