Vladimir Zunin
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Vladimir Zunin has a total of 104 co-authors. Here are the top co-authors by number of shared publications:
- Aleksandr Yu. Romanov
HSE University, 101000 Moscow, Russia
4 shared publications - Roman Solovyev
AlphaChip LLC., 124498 Moscow, Russia
2 shared publications Alan Lukežič
University of Ljubljana
1 shared publication- Aleksandr Aleksandrovich Amerikanov
HSE University, 101000 Moscow, Russia
1 shared publication - Alexander Murashov
National Research University of Electronic Technology (MIET), 124498 Moscow, Russia
1 shared publication - Alexander Stempkovskiy
AlphaChip LLC., 124498 Moscow, Russia
1 shared publication
Latest Publications
- Open Access
- 8 March 2026
- Published by MDPI AG in Technologies
- Vol. 14 (3) , 169
Machine Learning Methods for Fast Evaluation of Static IR Drop Effect
With the continuous scaling of semiconductor design technologies, evaluating static IR drop has become a critical bottleneck in the physical synthesis flow. This paper presents a machine learning-based framework that transforms the power delivery network (PDN) analysis problem into an image-to-image translation task using a U-Net architecture with MaxViT and EfficientNet encoders. By implementing a novel SPICE-to-image conversion flow and an asymmetric loss function, our method achieved a Top 3 ranking in the ICCAD 2023 Contest (Problem C). The experimental results demonstrate that the proposed model achieves a Mean Absolute Error (MAE) below V while providing up to a 30× speedup compared to NGSPICE.- 8 March 2026
- Published by MDPI AG in Technologies
- Vol. 14 (3) , 169
Open AccessMachine Learning Methods for Fast Evaluation of Static IR Drop Effect
With the continuous scaling of semiconductor design technologies, evaluating static IR drop has become a critical bottleneck in the physical synthesis flow. This paper presents a machine learning-based framework that transforms the power delivery network (PDN) analysis problem into an image-to-image translation task using a U-Net architecture with MaxViT and EfficientNet encoders. By implementing a novel SPICE-to-image conversion flow and an asymmetric loss function, our method achieved a Top 3 ranking in the ICCAD 2023 Contest (Problem C). The experimental results demonstrate that the proposed model achieves a Mean Absolute Error (MAE) below V while providing up to a 30× speedup compared to NGSPICE. - 12 May 2025
- Published by Springer Nature
- p. 357-383
The Second Visual Object Tracking Segmentation VOTS2024 Challenge Results
- 12 May 2025
- Published by Springer Nature
- p. 357-383
The Second Visual Object Tracking Segmentation VOTS2024 Challenge Results
- Open Access
- 2 April 2024
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Access
- Vol. 12, 48750-48763
Electronic Computer-Aided Design for Low-Level Modeling of Networks-on-Chip
This article proposes a Network-on-Chip (NoC) communication subsystem model on the basis of which the Electronic Computer-Aided Design (ECAD) architecture in the form of software is implemented. It makes it possible to automate the process of preparing and generating an HDL description of the NoC model in the Verilog language. It is shown that not in all cases it is required to model the entire NoC. Often, it is necessary to model its certain parts, such as a communication subsystem, routing algorithm, and traffic control system. The developed model allows modeling a parameterized NoC communication subsystem to obtain an estimate of the consumed logical blocks and registers required for prototyping the communication subsystem. All components of the communication subsystem are implemented as separate modules due to which the hardware costs for adding the necessary components for the study are reduced because of the absence of the need to completely rework the model program code every time. The effectiveness of using the developed ECAD and low-level modeling automation methods to study the work of routing algorithms for NoC topologies is demonstrated.
- 2 April 2024
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Access
- Vol. 12, 48750-48763
Open AccessElectronic Computer-Aided Design for Low-Level Modeling of Networks-on-Chip
This article proposes a Network-on-Chip (NoC) communication subsystem model on the basis of which the Electronic Computer-Aided Design (ECAD) architecture in the form of software is implemented. It makes it possible to automate the process of preparing and generating an HDL description of the NoC model in the Verilog language. It is shown that not in all cases it is required to model the entire NoC. Often, it is necessary to model its certain parts, such as a communication subsystem, routing algorithm, and traffic control system. The developed model allows modeling a parameterized NoC communication subsystem to obtain an estimate of the consumed logical blocks and registers required for prototyping the communication subsystem. All components of the communication subsystem are implemented as separate modules due to which the hardware costs for adding the necessary components for the study are reduced because of the absence of the need to completely rework the model program code every time. The effectiveness of using the developed ECAD and low-level modeling automation methods to study the work of routing algorithms for NoC topologies is demonstrated.
- Open Access
- 1 January 2023
- Published by Institute for System Programming of the Russian Academy of Sciences in Proceedings of the Institute for System Programming of the RAS
- Vol. 35 (5) , 81-90
The Open System for Storing and Processing of a Dataset of Combinational Circuits
. В этой статье представлено программное обеспечение с открытым исходным кодом для генерации, хранения и анализа комбинационных схем. Оптимизированы созданные ранее методы генерации комбинационных схем и сформирован датасет. Генерация комбинационных схем может осуществляться на различных устройствах. В приложении реализована возможность объединения сгенерированных наборов данных в единое хранилище (Synology Drive), а также анализа отказоустойчивости комбинационных схем с использованием различных методов их оценки. Предложены новые возможные методы оценки надежности комбинационных схем с использованием машинного обучения.
- 1 January 2023
- Published by Institute for System Programming of the Russian Academy of Sciences in Proceedings of the Institute for System Programming of the RAS
- Vol. 35 (5) , 81-90
Open AccessThe Open System for Storing and Processing of a Dataset of Combinational Circuits
. В этой статье представлено программное обеспечение с открытым исходным кодом для генерации, хранения и анализа комбинационных схем. Оптимизированы созданные ранее методы генерации комбинационных схем и сформирован датасет. Генерация комбинационных схем может осуществляться на различных устройствах. В приложении реализована возможность объединения сгенерированных наборов данных в единое хранилище (Synology Drive), а также анализа отказоустойчивости комбинационных схем с использованием различных методов их оценки. Предложены новые возможные методы оценки надежности комбинационных схем с использованием машинного обучения.