Mingyuan Sun
Mingyuan Sun has a total of 11 co-authors. Here are the top co-authors by number of shared publications:
- Guohui Ren
Southwest Branch of China National Petroleum Corporation Logging Company Ltd., Chongqing, China
2 shared publications - Jun-Jie Wang
State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu, China
2 shared publications - Kai Tang
China National Logging Corporation, China
2 shared publications - Xin-Di Zhao
Southwest Branch of China National Petroleum Corporation Logging Co., Ltd., Chongqing 401100, China
2 shared publications - Yang Liu
University of Electronic Science and Technology of China
2 shared publications - Hongzhe Wang
School of Integrated Circuit Science and Engineering, Universityof Electronic Science and Technology of China, Chengdu, Sichuan, China
1 shared publication
Latest Publications
- Open Access
- 17 November 2023
- Published by Association for Computing Machinery (ACM)
- p. 236-240
A Programmable Logic-in-Memory Architecture Based on 22nm Fully DepletedSilicon on Insulator Technology
Logic-in-memory (LIM) is an attractive approach to overcome the limitations of the conventional von Neumann architecture, especially in big data applications. Recently, many works have been focused on implementing Boolean logic or majority gate logic in memory using non-volatile storage devices. This work presents a programmable logic-in-memory (PLIM) architecture based on 22nm Fully Depleted Silicon on Insulator (FD-SOI) technology, which can map XOR, AND, and OR logic operations. Additionally, the architecture can be independently programmed in the column direction. The proposed architecture introduces a minimal hardware overhead and enables logic programming operations through simple manipulation.
- 17 November 2023
- Published by Association for Computing Machinery (ACM)
- p. 236-240
Open AccessA Programmable Logic-in-Memory Architecture Based on 22nm Fully DepletedSilicon on Insulator Technology
Logic-in-memory (LIM) is an attractive approach to overcome the limitations of the conventional von Neumann architecture, especially in big data applications. Recently, many works have been focused on implementing Boolean logic or majority gate logic in memory using non-volatile storage devices. This work presents a programmable logic-in-memory (PLIM) architecture based on 22nm Fully Depleted Silicon on Insulator (FD-SOI) technology, which can map XOR, AND, and OR logic operations. Additionally, the architecture can be independently programmed in the column direction. The proposed architecture introduces a minimal hardware overhead and enables logic programming operations through simple manipulation.
- Open Access
- 17 November 2023
- Published by Association for Computing Machinery (ACM)
- p. 241-244
FPGA-implemented Memristor-based Transient Chaotic Neural Network for AES Edge Encryption
In response to the escalating demand for edge encryption in the big data era, we introduce the implementation of the Memristor-based Transient Chaotic Neural Network (MTCNN) on FPGA. This innovative approach aims to elevate the security of key generation for the Advanced Encryption Standard (AES) algorithm. Through meticulous mapping and optimization of MTCNN-AES encryption algorithm on FPGA, we achieve efficient edge encryption. Notably, the FPGA-implemented MTCNN-AES features a key space 22 orders of magnitude larger than traditional AES, underscoring its substantial resilience against brute-force attacks. The proposed approach aligns with federal information processing standards, emphasizing its reliability, robustness and randomness.
- 17 November 2023
- Published by Association for Computing Machinery (ACM)
- p. 241-244
Open AccessFPGA-implemented Memristor-based Transient Chaotic Neural Network for AES Edge Encryption
In response to the escalating demand for edge encryption in the big data era, we introduce the implementation of the Memristor-based Transient Chaotic Neural Network (MTCNN) on FPGA. This innovative approach aims to elevate the security of key generation for the Advanced Encryption Standard (AES) algorithm. Through meticulous mapping and optimization of MTCNN-AES encryption algorithm on FPGA, we achieve efficient edge encryption. Notably, the FPGA-implemented MTCNN-AES features a key space 22 orders of magnitude larger than traditional AES, underscoring its substantial resilience against brute-force attacks. The proposed approach aligns with federal information processing standards, emphasizing its reliability, robustness and randomness.