Yiwei Chang

Remote Direct Memory Access (RDMA) technology provides a low-latency, high-bandwidth, and CPU-bypassed method for data transmission between servers. Recent works have proved that multipath transmission, especially packet spraying, can avoid network congestion, achieve load balancing, and improve overall performance in data center networks (DCNs). Multipath transmission can result in out-of-order (OOO) packet delivery. However, existing RDMA transport protocols, such as RDMA over Converged Ethernet version 2 (RoCEv2), are designed for handling sequential packets, limiting their ability to support multipath transmission. To address this issue, in this study, we propose ORNIC, a high-performance RDMA Network Interface Card (NIC) with out-of-order packet direct write method for multipath transmission. ORNIC supports both in-order and out-of-order packet reception. The payload of OOO packets is written directly to user memory without reordering. The write address is embedded in the packets only when necessary. A bitmap is used to check data integrity and detect packet loss. We redesign the bitmap structure into an array of bitmap blocks that support dynamic allocation. Once a bitmap block is full, it is marked and can be freed in advance. We implement ORNIC on a Xilinx U200 FPGA (Field-Programmable Gate Array), which consumes less than 15% of hardware resources. ORNIC can achieve 95 Gbps RDMA throughput, which is nearly 2.5 times that of MP-RDMA. When handling OOO packets, ORNIC’s performance is virtually unaffected, while the performance of Xilinx ERNIC and Mellanox CX-5 drops below 1 Gbps. Moreover, compared with MELO and LEFT, our bitmap has higher performance and lower bitmap block usage.

Software-defined networking (SDN), with its decoupled control and data planes, offers greater flexibility compared to traditional networks, making it ideal for modern, dynamic network environments. This paper proposes a consistent, protocol-independent, and flexible flow configuration system within a 100Gbps reconfigurable match tables (RMT) pipeline enhancing the capability of the open-source NIC framework Corundum for SDN on Field-Programmable Gate Array (FPGA). Our prototype supports concurrent Write, Read, and Delete operations for exact, wildcard, and stateful matching, with a single thread in our server handling up to 719.42K, 751.88K, and 1.45M flows per second for Write, Read, and Delete operations, respectively, which is sufficient for production networks. Additionally, managing a single flow table requires less than 0.1% area overhead on the Xilinx AU200 platform, and each entry is handled in a single clock cycle without blocking the processing pipeline ensuring timely and consistent flow configurations. In conclusion, our prototype is highly scalable, resource-efficient, and efficient.

Field-programmable gate arrays (FPGAs) are key accelerators in cloud data centers due to their parallelism and programmability. However, challenges such as low hardware utilization and high virtualization overhead persist. This brief presents RosebudVirt, a high-performance and partially reconfigurable FPGA virtualization framework tailored for multitenant networks. It enhances the original Rosebud by introducing single-root I/O virtualization (SR-IOV) support, partitioning the PCIe-attached FPGA device into multiple physical functions (PFs) and virtual functions (VFs) accessible to the linux kernel via PF and VF drivers. This facilitates direct mapping among tenants, VFs, and reconfigurable packet-processing units (RPUs) within the FPGA. RosebudVirt achieves near-native throughput with $<$ 1% area overhead and increases hardware utilization by up to 7.6 times by additional VF drivers and network interfaces. What is more, RosebudVirt is compatible with Kubernetes and Docker.