Milan Dinčić

This paper proposes an SQNR-based method for the design of bfloat16-inspired 16-bit floating-point representations for ReLU activations. The method exploits the analogy between floating-point formats and piecewise-uniform quantizers and uses SQNR as a performance metric to evaluate alternative bit allocations between the significand and exponent fields for a given input probability density function (PDF). For ReLU activations, the PDF is derived from a Laplacian pre-activation model, showing that ReLU outputs are non-negative and that the sign bit in bfloat16 is redundant. The redundant bit is therefore reallocated within the fixed 16-bit budget, yielding two representations: FP16^I, with the bit added to the significand, and FP16^II, with the bit added to the exponent. Using the ReLU PDF, closed-form SQNR models are obtained for both representations and used to characterize their performance relative to bfloat16. An analysis over a wide range of input variances shows that FP16^I provides a 6.02 dB SQNR improvement over bfloat16, whereas FP16^II maintains the bfloat16 SQNR level within a substantially wider variance range. These SQNR models are further applied to guide the selection between FP16^I and FP16^II for CNN training based on the observed variance range of pre-ReLU activations. It is demonstrated that replacing the bfloat16 ReLU representation with the selected alternative in a bfloat16-quantized CNN results in training performance closer to that of the FP32-based configuration.

Resilient integrated circuits (ICs) are essential for safety- and mission-critical applications, where hardware faults can result in costly damage or even loss of lives. A resilient IC is designed to detect, tolerate, and adapt in real time to different faulty scanarios, maintaining correct functionality under varying operating and environmental conditions. Specialized sensing and analytics engines embedded in the chip play a central role in resilient ICs by providing real-time insight into the overall state, i.e., "health", of the chip. This paper presents an overview of commonly used on-chip sensors for IC status monitoring, and discusses fundamental design requirements for on-chip processing of sensor-generated data.

Recent advancements in neural network (NN) hardware and software have introduced 8-bit Floating-Point (FP8) format as promising candidate for reducing memory usage and computational overhead. This article investigates the potential for further compressing FP8) data by applying Golomb-Rice (GR) coding. In the FP8 format, the 8 bits are allocated to represent the sign, exponent and mantissa using natural binary encoding. To achieve efficient compression, the GR code, a variable-length, lossless coding scheme, is applied exclusively to the exponent bits. In this way, data storage savings could be achieved, which can be very significant when the large amount of data has to be stored, such as storing NNs.

The Special Session on Hardware and Software Solutions for Edge AI Applications at the IEEE MIEL 2025 is being organized as part of the EU-funded Horizon Twinning project “Twinning for Excellence in Adaptive Edge AI” (acronym: AIDA4Edge) [1]–[3]. The project is coordinated by the Faculty of Electronic Engineering, University of Niš (FEEUNI), in partnership with the Leibniz Institute for High Performance Microelectronics (IHP), University of Manchester (UoM), and University of Ferrara (UNIFE). AIDA4Edge started on October 1, 2024, and will run for three years. Its main goal is to strengthen scientific, networking and research management capacity of FEEUNI through an intensive collaboration with the advanced partners, enabling FEEUNI to achieve scientific and innovation excellence in the field of Edge AI. Fig. 1 shows the AIDA4Edge logo, and logos of funding institutions.

The application of compression techniques, such as quantization and pruning, to reduce neural network weight size and complexity is gaining momentum due to the significant savings they provide in both hardware and software resources, particularly important for edge devices with limited capabilities. To fully leverage the advantages of these techniques, their design should account for the amplitude dynamics and the probability distribution of the parameters to be compressed. Therefore, it is essential to analyze the statistical characteristics of these parameters prior to compression. Although this type of analysis has been extensively conducted in the context of Artificial Neural Networks (ANNs), it has received limited attention in the case of Spiking Neural Networks (SNNs). Motivated by this gap, this paper examines the statistical properties of the weights of an SNN trained on the DVS128 Gesture dataset. The results of this analysis are valuable not only for enabling a well-founded selection and effective design of appropriate quantization models, but also for supporting the efficient application of pruning techniques, which could benefit from using synaptic weight histograms as valuable guiding information.

The 32-bit floating-point (FP32) format has many useful applications, particularly in computing and neural network systems. The classic 32-bit fixed-point (FXP32) format often introduces lower quality of representation (i.e., precision), making it unsuitable for real deployment, despite offering faster computations and reduced computational cost, which positively impacts energy efficiency. In this paper, we propose a switched FXP32 format able to compete with or surpass the widely used FP32 format across a wide variance range. It actually proposes switching between the possible values of key parameters according to the variance level of the data modeled with the Laplacian distribution. Precision analysis is achieved using the signal-to-quantization noise ratio (SQNR) as a performance metric, introduced based on the analogy between digital formats and quantization. Theoretical SQNR results provided in a wide range of variance confirm the design objectives. Experimental and simulation results obtained using neural network weights further support the approach. The strong agreement between the experiment, simulation, and theory indicates the efficiency of this proposal in encoding Laplacian data, as well as its potential applicability in neural networks.

This paper provides a simple method for efficient performance evaluation of floating-point (FP) formats, addressing the challenge of implementing DNN (deep neural network)-based sensor nodes and edge measurement devices. Since resource constraints are imposed in such scenarios, the 32-bit FP format, standardly used for DNN implementation, is unsuitable, and the alternative is found in lower-resolution FP formats which leads to certain performance degradation. Hence, an efficient mechanism for performance evaluation of different FP formats is needed to examine the influence of resolution decreasing. Existing methods utilize the analogy between FP formats and piecewise uniform quantizers (PUQs), using the signal-to-quantization noise ratio (SQNR) of the PUQ to express the performance of FP formats. However, the high complexity of SQNR calculations, involving sum with many terms (e.g. 254 terms for FP formats with an 8-bit exponent), poses a significant challenge. This paper’s main contribution is the significant simplification of the SQNR expression for Gaussian-distributed data, reducing the number of sum terms from 254 to just 5 with minimal accuracy loss, allowing for simple and efficient performance evaluation of FP formats. Major findings include an in-depth analysis of the probability distribution across PUQ segments, a closed-form expression for identifying the highest probability segment, and an evaluation of the SQNR approximation’s accuracy. These findings provide a foundational basis for implementing intelligent DNN-based measurement systems, with applications extending to computing, signal processing, and other fields utilizing FP formats.

Pseudorandom absolute position encoders represent an advanced version of the widely used absolute position encoders, particularly suitable for high-resolution angular position measurement. This paper presents a detailed performance analysis of the pseudorandom absolute position encoder with embedded serial pseudorandom/natural code converter, focusing on the maximum operating frequency and the absolute error in angular position measurement. The generalized analysis, applicable to various resolution values, represents a significant contribution of the paper. Determining the maximum operating frequency involves a detailed analysis of propagation delays in the serial code converter circuit. It is demonstrated that encoder resolution profoundly impacts performance, with a dual effect: higher resolution decreases the absolute error but also reduces the maximum operating frequency, necessitating the determination of the most suitable resolution value for each specific application. In addition to its theoretical importance, the generalized analysis aids practical application by facilitating performance calculations and the selection of the most suitable resolution for specific applications. The performance evaluation was conducted for code converters implemented using the widely used 74LVC logic circuits, considering a 6-bit converter as a representative example of converters with a single XOR logic gate in the feedback loop of the shift register, and an 8-bit converter as a representative example of serial converters with three XOR logic gates in the feedback loop. By applying the proposed analysis, the maximum clock frequency was determined to be 29.85 MHz for both resolution values (6 and 8 bits). Simulations in NI Multisim software validate the performed analysis, showing a strong correlation between simulation and theoretical results.

U radu su predstavljene performanse DPCM (Differential Pulse Code Modulation) sistema sa fiksnim Lloyd Max kvantizerom i prediktorom prvog reda. Sistem je primenjen za obradu snimljenog EKG (ElectroCardioGram) signala. Sagledane su mogućnosti korigovanja parametara sistema kao što su opseg kvantizera i vrednosti koeficijenta prediktora sa ciljem poboljšanja performansi sistema. Uočen je efekat propagacije greške nastale usled kvantizacije i predikcije.