Manoj Sharma

The main purpose of this paper is to obtain the solution of fractional order linear dierential equation in RLC Circuit by using a Mittag-Leffler-kummer function. The solution of the fractional linear differential equation of the RLC circuit comes in the form of the Mittag-Leffler function.

We report growth and characterization of n-Si/p-SnO _x heterojunction using RF sputtering for deposition of p-type SnO _x under controlled growth oxygen pressure over n-type silicon (Si) wafer. The heterojunction properties of Si/SnO _x were varied by controlling the growth oxygen pressure of SnOx. Several characterization techniques, including PL (photoluminescence), AFM (atomic force microscopy), FESEM (field emission scanning electron microscopy), XRD, I-V characteristics and Hall measurement, were conducted to analyze the structural, optical, and electrical properties of the n-Si/p-SnOx heterojunction. The knee voltage (V _knee ), or cut-in voltage, was calculated by analyzing the gradient of the dark current-voltage (J-V) curves when the bias was applied in the forward direction. The V _knee values for type-I, type-II, and type-III n-Si/p-SnO _x heterojunctions were determined to be 0.62 V, 0.84 V, and 1.0 V, respectively. The ideality factors (n ₁ and n ₂ ) were determined to be 1.52, 2.22, 3.52, and 8.41, 9.31, 10.34, respectively, for various heterojunction types. The reverse saturation current densities, J ₀₁ and J ₀₂ ranging from approximately 10 ⁻⁷ to 10 ⁻⁶ A/cm ² , and 10 ⁻⁵ to 10 ⁻⁴ A/cm ² , respectively. The objective of this experimental work is to investigate especially, the prospect of silicon /metal-oxide (Si/SnOx) based heterojunction to be used as optical sensors with tunable optoelectronic properties of SnOx.

FFT is one of the critical component required to implement a real time system on FPGAs. The FFT implementation on FPGA consume major proportional area on the limited resource in FPGA specifically the specialized DSP blocks embedded in FPGA architecture. This reduces the resources availability for other required functionalities. Authors in this work have proposed an efficient pipelined implementation of FFT targeting FPGA which reduces the DSP blocks and efficiently decompose the input signal into its sine and cosine components. Vertex 6 family of Xilinx is used to prototype and verify the correctness of the proposed design. The functional verification and implementation on the FPGA proved the efficient proposed design.

Fourier transform is a crucial signal processing tool, as it can decompose a signal into its sine and cosine components, it provides a different vision to process input signal. Authors have proposed an area optimized FFT for multimedia applications on FPGA. It is designed focusing on device utilization by optimal structural reusing. Proposed design are verified, synthesized and mapped on Xilinx Virtex6 device.

In this paper authors have presented a design and experimentation evaluation of circuit optimization inspired by adiabatic logic processing. The reported work inherent the power benefits associated with adiabatic charge transfer process. Simultaneously it also addresses an important issue of optimizing the high transistor count as required in traditional adiabatic logic families. Therefore the proposed hybrid adiabatic logic family not-only optimize the circuit area along with power but also it removes the requirement of dual polarity inputs for circuit actuation. Different circuits are optimized and implemented using the reported work in 180nm technology with trapezoidal power clock. The results obtained are compared with circuits available in previous works. The functional verification and result measurements proved the advantages associated with the proposed circuit optimization for energy efficient implementation for very-large scale integrated (VLSI) circuits

Previously, authors have proposed CPLAG and MCPLAG circuits extracting benefits of CPL family implemented based upon semiadiabatic logic for low power VLSI circuit design along with gating concept. Also authors have communicated RCPLAG circuits adding another dimension of reconfigurability into CPLAG/MCPLAG circuits. Moving ahead, in this paper, authors have implemented/reconfigured RCPLAG universal Nand/And gate and universal Nor/Or gate for extracting behavior of dynamic positive edge triggered DFF. Authors have also implemented Adder/Subtractor circuit using different techniques. Authors have also reported modification in PFAL semiadiabatic circuit family to further reduce the power dissipation. Functionality of these is verified and found to be satisfactory. Further these are examined rigorously with voltage, , temperature, and transistor size variation. Performance of these is examined with these variations with power dissipation, delays, rise, and fall times associated. From the analysis it is found that best operating condition for DFF based upon RCPLAG universal gate can be achieved at supply voltage lower than 3V which can be used for different transistor size up to 36μm. Average power dissipation is 0.2μW at 1V and 30μW at 2V at 100ff 25°C approximately. Average power dissipated by CPLAG Adder/Subtractot is 58μW. Modified PFAL circuit reduces average power by 9% approximately.