Filippo Ferraro

We apply the transfer matrix method (TMM) to model the evolution of light spectral reflectivity during reactive ion etching of SiGe heterostructures used in electro-absorption modulators. The simulated reflectivity as a function of etch depth shows excellent agreement with in situ light spectral reflectometry measurements, enabling identification of wavelength ranges most sensitive to changes in the quantum-well (QW) stack. For Ge-rich SiGe (∼80% Ge), both modeling and experiment indicate a sensitivity window centered near 500 ± 50 nm, where the QW heterostructure exhibits a distinct spectral signature. We further show that introducing a thin SiGe etch-contrast layer (ECL) with ∼10% Ge concentration offset from the strain-relaxed buffer composition produces a clear reflectivity response that simplifies end point determination. These results demonstrate how TMM-assisted wavelength selection and ECL engineering can enhance the robustness of etch end point algorithms for advanced SiGe photonic device fabrication.

We report on the design, modeling, and measurements of high-speed, silicon-contacted, waveguide-coupled Germanium-on-Silicon (Ge/Si) avalanche photodiodes (APDs) fabricated on 300 mm Silicon On insulator (SOI) wafers. The devices achieve a peak 3-dB bandwidth (BW) exceeding 100 GHz and maintain 70 GHz BW at a responsivity of 2 A/W in both the O- and C-bands, at a relatively low reverse bias of 7 V. These results demonstrate the strong potential of Ge/Si APDs to be used for next-generation short-reach optical interconnects targeting 400 Gbps per lane operation.

We present a novel compact asymmetric bent directional coupler polarization beam splitter (PBS) fabricated on a silicon-on-insulator (SOI) platform using third-order polynomial interconnected circular (TOPIC) bends. The TOPIC bend design provides continuous curvature and curvature derivatives throughout the structure, which minimizes mode transition losses at connection interfaces. This approach allows for the implementation of tight bend radii to enhance extinction ratio performance without compromising insertion loss, thereby resolving the conventional trade-off limitation in bent-coupler PBS designs. The device performance was characterized through cascaded measurements involving up to 40 PBS units, with single-device loss parameters extracted via linear regression analysis. Comprehensive wafer-level testing across 61 dies confirmed excellent design reproducibility and manufacturing tolerance. The optimized PBS achieves insertion losses as low as 0.017$\pm$0.007 dB for TE and 0.019$\pm$0.018 dB for TM polarizations, accompanied by extinction ratios of 25.5$\pm$0.5 dB and 29.6$\pm$6.1 dB, respectively, at 1295 nm wavelength. These results establish new performance benchmarks for silicon photonic PBS devices and demonstrate significant potential for advanced polarization-handling applications in integrated photonic systems.

Recent developments in system-on-wafer high-performance compute systems have delivered promising results for alleviating the memory wall encountered in AI/ML training workloads. This is achieved by integrating multiple XPUs on the same interposer substrate. It is expected that performance can scale further by replacing the electrical interface with an optical variant. In this paper, we study the thermal challenges this concept brings for Si photonic disk modulators, a key component of the optical transceiver. Because of the highly integrated nature of the system, thermal crosstalk is especially a concern, as well as heater efficiency for thermal tuning. Detailed, experimentally calibrated simulations reveal a loss of heater efficiency between 42–62% after hybrid bonding of the electrical IC (EIC) on the photonic IC (PIC). This loss can partially be offset by introducing a new thermal isolation feature called TOPCUT, which blocks vertical heat conduction and increases efficiency by 25%. Alternatively, co-design of the EIC back-end-of-line layers and the PIC layout to ensure low metal density directly above the device can be done to gain 12% heater efficiency. Thermal simulations of a fully populated interposer wafer reveal extremely low thermal crosstalk between tiles, but significant crosstalk inside a single tile. Studies predict a spatial gradient of 12 K/mm and temporal gradient of 1.78 K/ms in the PIC due to XPU power map.

In this paper, we present a collective photonic integrated circuits (PIC) die-to-wafer dielectric bonding process, enabling silicon nitride (SiN) waveguide-based die-to-wafer evanescent coupling with insertion losses (IL) of 0.16 ±0.06 dB at optical O-band 1310 nm wavelength. This SiN evanescent coupling is of great significance and offers integration flexibility to effectively reduce optical coupling loss and enable higher-density optical connectivity compared to conventional edge coupling optical fiber arrays. The collective die-to-wafer bonding process enhances manufacturing efficiency by enabling high throughput, reducing handling steps, and lowering overall production costs. Besides, the evanescent coupling misalignment tolerance is up to 2 μm, which can mitigate alignment sensitivity and packaging difficulties. This advancement supports high-volume, low-latency, lower-energy-consumption optical I/O, paving the way for optically interconnected 300 mm wafer-scale multi-XPU compute systems for high-performance AI/ML computing.