Sicheng Han

This article presents a compact distributed power amplifier (DPA) for high-data-rate communication in 40-nm standard CMOS technology. By leveraging high-power-density cells, this DPA breaks the conventional compromise among output power, area, and bandwidth. With the adoption of the Ruthroff-type distributed balun, balanced signals are efficiently combined across a broad bandwidth in a compact area. Furthermore, the implementation of a twisted and embedded output matching network (OMN) ensures resonance with parasitic capacitance while avoiding extra area overhead. The DPA achieves a 16.6-dB gain and delivers an output power of 19 dBm with 21.4% power-added efficiency (PAE) at peak ${P} _{\text {sat}}$ , covering the bandwidth of 1.5–23.5 GHz from a 1.8-V supply. It reaches up to 150.5-Gb/s data rate with 14.4-dBm average output power in 128-quadrature-amplitude-modulation (QAM). In addition, this study supports 256-QAM at a data rate of over 110 Gb/s.

This article presents a wideband digitally-controlled variable gain amplifier (VGA) with process voltage and temperature (PVT)-robust decibel-linear (dB-linear) characteristic, including two cascaded VGA cells, an exponential generator, a self-compensated control voltage generator and a self-adaptive current and voltage bias. The VGA cell is realized by a folded Gilbert-cell and it achieves a 2.4 GHz gain-independent bandwidth (BW). The exponential generator is realized by a parasitic bipolar transistor and it achieves a dB-linear gain control range of 59.7 dB with a gain error lower than 0.39 dB. A self-compensated control voltage generator is proposed to optimize the dB-linear gain response PVT robustness. The nonidealities that deteriorate the PVT robustness are analyzed and optimized. A self-adaptive current and voltage bias is proposed to alleviate the gain drift caused by the channel length modulation effect. Under PVT variations, the gain drift of the VGA is lower than 5.12 dB and its gain slope drift is lower than 3.99%. Based on the reconfigurability of the VGA’s dB-linear gain response, an automatic calibration flow is proposed to eliminate the gain response deviations between chips. Fabricated in a 40 nm standard CMOS process, the proposed VGA consumes 6.26 mW dc power under a 1.2-V supply voltage (excluding the output buffer) and occupies an active area of 0.036 mm2.

This article presents an ultra-wideband (UWB) low noise amplifier (LNA) with $g_{m}$ -assisted-feedback noise suppression technique for multi-band wireless communication. Compared with the traditional resistive feedback (RF) and source-follower feedback wideband LNAs, the proposed LNA blocks the noise current from the feedback resistor with a simple additional $g_{m}$ -cell, thus alleviating the $S_{11}$ -NF design tradeoff in the traditional structures. A source coupling transformer is also utilized to create $g_{m}$ -boosting and maintain a wideband flat gain. Fabricated in a 40-nm bulk CMOS process, the LNA prototype achieves a measured operating bandwidth (BW) of 1–21 GHz, measured NF of 1.95–3.1 dB, and $S_{21}$ of 20.6–22.4 dB, while consuming 21.6 mA from a 1.2-V power supply. It also supports UWB modulation signals with a data rate of 140 Gb/s. The proposed LNA reports the lowest NF among the recently reported bulk CMOS UWB LNAs.

A wideband low‐noise amplifier (LNA) for long‐term evolution applications is presented. A capacitive cross‐coupled common‐gate in combination with current‐bleeding common‐source topologies is adopted for wideband input matching, high gain and low noise figure (NF). Inter‐cascade inductors are adopted to cancel the inter‐stage parasitics, which extend input matching and operational bandwidth to higher frequency with additional NF reduction. Implemented in a 0.18 µm CMOS technology, the proposed wideband LNA shows a voltage gain of 17 dB, a NF of < 2.5 dB, | S ₁₁ | of higher than 10 dB and a maximum IIP3 of + 1.52 dBm over the frequency range of 0.7–2.7 GHz while consuming 7.5 mA from a 1.8 V supply.

A full frequency band active RF tracking filter design for a digital TV tuner is implemented for the first time. By combined control of the G_m and C values in the biquad of the G_m-C filter, the proposed tracking bandpass filter satisfies full frequency band tuning while maintaining narrow bandwidth. The G_m cell of the tracking filter is based on a dynamic source degenerated differential pair with optimised transistor size ratio, which provides good linearity and high-frequency operation. The fabricated tracking filter based on a 0.13 µm CMOS process shows 48–780 MHz tracking range with 15–60 MHz bandwidth, more than 50 dB of third-order harmonic rejection, 14 dB unwanted signal rejection at N+6 channel offset, and a maximum IIP3 of 3.8 dBm at 4.7 dB gain while drawing 30 mA from a 1.2 V supply.