Matheus S. Pereira

Convolutional Neural Networks (CNNs) are increasingly used for on-board image classification in satellites and aerial vehicles, but their deployment on SRAM-based FPGAs and All-Programmable System-on-Chip (APSoC) is limited by radiation-induced faults. This work introduces URSA, a reconfigurable Systolic Array (SA) accelerator for CNN inference implemented on AMD Xilinx Zynq-7000 devices. URSA allows design-time configurability of array geometry and memory organization, enabling the systematic experimental evaluation of how these architectural choices interact with fault-tolerance techniques to determine system-level reliability. A heavy-ion irradiation campaign at the SAFIIRA facility evaluated multiple URSA variants against naive and Arm-based baselines, considering Triple Modular Redundancy (TMR), configuration scrubbing, and Error Detection and Correction (EDAC). Results show that URSA consistently outperforms baselines, that combining TMR and scrubbing provides the most effective resilience improvements, and that OCM-based configurations outperform BRAM-based ones due to reduced programmable logic exposure. From these results, four architectural design guidelines are derived, providing quantified, experimentally validated recommendations for systolic-array CNN accelerators in radiation-prone environments.

As Convolutional Neural Networks (CNNs) implemented on All Programmable System on Chips (APSoCs) are increasingly adopted in space mission-critical systems due to their flexibility and parallelism, selecting a fault-tolerant design that balances reliability, area, and power is essential to address radiation-induced faults and resource constraints. However, the literature offers limited exploration of the combined use of multiple fault-tolerance techniques within a single AI accelerator, making it difficult to identify the most effective strategies. To address this, we propose a generalizable design flow and apply it to the ZynqNet accelerator which is generated using High-Level Synthesis (HLS). ZynqNet implements a 4-layer CNN trained on the SAT-6 dataset for aerial image classification. The goal is to evaluate the impact of several fault-tolerance strategies applied at different levels of architectural granularity based on Triple Modular Redundancy (TMR), including Modular TMR (MTMR), Coarse-Grained TMR (CGTMR), and Distributed TMR (DTMR), targeting bit flips in the configuration memory (CRAM) of the Field-Programmable Gate Array (FPGA). Additionally, memory scrubbing was implemented to correct and prevent the accumulation of CRAM faults over time, while error detection and correction codes (EDAC) were employed to protect volatile data stored in caches. The evaluation was validated through both fast, low-cost emulated fault injection and real heavy-ion irradiation experiments. Results show that the combination of DTMR, EDAC, and CRAM scrubbing at a reliability above 90% improves the expected mission image by 4.8× in emulation and 6.31× in irradiation.

This study examines the performance of two Convolutional Neural Networks (CNNs) designed for aerial image classification in the presence of radiation-induced bit-flips. We modify these CNNs by adjusting parameters such as quantization and parallelism to facilitate their implementation using the FINN inference engine, which is optimized for the AMD/Xilinx FPGAs. The aim is to evaluate the impact of different quantization levels, network topologies, and architectural parallelism on area, computational performance, and reliability in the presence of soft-errors. Emulated fault injection and heavy ion irradiation were performed. The results indicate that the same CNN topology can exhibit up to a 2.7× difference in Mean Fluence to Failure (MΦTF) by altering quantization and architectural parallelism. The findings demonstrate that higher dependability can be obtained by carefully combining a suitable CNN topology with optimized quantization and architectural parallelism.

The U-shaped Metal-Oxide-Semiconductor Field-Effect Transistor (UMOS or trench FET) is one of the most widely used semiconductor power devices worldwide, increasingly replacing the traditional vertical double-diffused MOSFET (DMOSFET) in various applications due to its superior electrical performance. However, a detailed experimental comparison of ion-induced Single-Event Burnout (SEB) in similarly rated silicon (Si) UMOS and DMOS devices remains lacking. This study presents a comprehensive experimental comparison of ion-induced charge collection mechanisms and SEB susceptibility in similarly rated Si UMOS and DMOS devices. Charge collection mechanisms due to alpha particles from ²⁴¹Am radiation source are analyzed, and SEB cross sections induced by heavy ions from particle accelerators are directly compared. The implications of the unique gate structure of Si UMOSFETs on their reliability in harsh radiation environments are discussed based on technology computer-aided design (TCAD) simulations.

The trench gate or U-groove MOSFET (UMOSFET) has become widely adopted as a semiconductor device globally, gradually replacing the traditional vertical double-diffused MOSFET (DMOSFET) in many applications. Evaluating the reliability of UMOSFETs regarding neutron-induced radiation effects is crucial for understanding their response to ubiquitous atmospheric neutrons. This study presents comparative experimental and computational results of Single-Event Effects induced by monoenergetic fast neutrons in UMOS and DMOS power transistors. Experiments demonstrate that UMOSFETs exhibit premature particle-induced avalanche multiplication effects compared to similarly rated DMOSFETs, which may favor destructive radiation effects, such as Single-Event Burnout, when operating in the terrestrial radiation environment.

The vulnerability of prominent silicon-based U-shaped Metal-Oxide-Semiconductor Field Effect Transistors (UMOSFET) to destructive radiation effects when operating in terrestrial atmospheric environments is addressed. It is known that secondary particles from nuclear reactions between atmospheric neutrons and the constituent materials of electronic devices can trigger Single-Event Burnout (SEB) destructive failure in power MOSFETs. The susceptibility of UMOSFETs to SEBs induced by atmospheric neutrons in accelerated tests are compared to that of similarly rated traditional Double-diffused MOSFET (DMOSFET) counterparts. Computational simulations are conducted to elucidate failure mechanisms and propose strategies to potentially enhance the survivability of next-generation UMOSFETs in high-reliability power systems operating on Earth.

Radiation effects on electronic devices represent a major concern in applications for harsh environments, such as aerospace and nuclear facilities. This article presents a review of fundamental aspects of radiation effects on semiconductors, with a primary focus on Single-Event Effects. It discusses charge collection models, destructive effects, applications in detectors, and impacts on digital devices, drawing from recent research findings.

The vulnerability of prominent silicon-based U-shaped Metal-Oxide-Semiconductor Field Effect Transistors (UMOSFET) to destructive radiation effects when operating in terrestrial atmospheric environments is addressed. It is known that secondary particles from nuclear reactions between atmospheric neutrons and the constituent materials of electronic devices can trigger Single-Event Burnout (SEB) destructive failure in power MOSFETs. The susceptibility of UMOSFETs to SEBs induced by atmospheric neutrons in accelerated tests are compared to that of similarly rated traditional Double-diffused MOSFET (DMOSFET) counterparts. Computational simulations are conducted to elucidate failure mechanisms and propose strategies to potentially enhance the survivability of next-generation UMOSFETs in high-reliability power systems operating on Earth.