Kannan Nithin Kariyankattil Velukutty
Research Subjects
Kannan Nithin Kariyankattil Velukutty has a total of 28 co-authors. Here are the top co-authors by number of shared publications:
- Deepa Sundararajan
Department of Physics, Government College of Engineering, Salem, India
3 shared publications - Munuswamy Premalatha
Department of Mathematics, Vel Tech Rangarajan Dr. Sagunthala R&D Institute of Science and Technology, Avadi, Chennai, India
2 shared publications - Muthuraman Ramaiah Krishnappa
Sri Ramakrishna Engineering College, Tamil Nadu, Coimbatore, India
2 shared publications - N. R. Govinthasamy
Department of Electrical and Electronics Engineering, Dr.N.G.P. Institute of Technology, Coimbatore, India
2 shared publications - Prabu Pachiyannan
Information Systems Department, College of Computer and Information Sciences, Imam Mohammad Ibn Saud Islamic University (IMSIU), Riyadh, Saudi Arabia
2 shared publications - Selligoundanur Subramaniyam Sivaraju
Department of Electrical and Electronics Engineering, RVS College of Engineering and Technology, Kannampalayam, Coimbatore, India
2 shared publications
Latest Publications
- 16 October 2025
- Published by Springer Nature in International Journal of System Assurance Engineering and Management
- Vol. 17 (3) , 649-661
Performance analysis of modern EV batteries: efficiency, longevity, and future innovations
- 16 October 2025
- Published by Springer Nature in International Journal of System Assurance Engineering and Management
- Vol. 17 (3) , 649-661
Performance analysis of modern EV batteries: efficiency, longevity, and future innovations
- Open Access
- 1 August 2024
- Published by European Alliance for Innovation n.o. in EAI Endorsed Transactions on Energy Web
- Vol. 11
ASIC Design and Implementation of 32 Bit Arithmetic and Logic Unit
Low power techniques are becoming more important as portable digital applications expand quickly and demand high speed and low power consumption. The ALU is the most crucial and essential component of a central processing unit, as well as numerous embedded systems and microprocessors. Designing a 32-bit ALU that combines an arithmetic unit and a logical unit is the task at hand. The logic unit will do logic operations AND, OR, XOR, and XNOR with the aid of the recommended CMOS technology, while the arithmetic unit will do the arithmetic operations addition, subtraction, increment, and buffering operation. The arithmetic unit is constructed using the 4x1 MUX, 2x1 MUX, and full adder, and the 4x1 MUX, required logic gates, and 4x1 MUX are employed to create the logical unit. Using Cadence Virtuoso Gpdk 180nm Technology, the results of the simulation of the 32-bit ALU, the ideal delay, and the Power were calculated.
- 1 August 2024
- Published by European Alliance for Innovation n.o. in EAI Endorsed Transactions on Energy Web
- Vol. 11
Open AccessASIC Design and Implementation of 32 Bit Arithmetic and Logic Unit
Low power techniques are becoming more important as portable digital applications expand quickly and demand high speed and low power consumption. The ALU is the most crucial and essential component of a central processing unit, as well as numerous embedded systems and microprocessors. Designing a 32-bit ALU that combines an arithmetic unit and a logical unit is the task at hand. The logic unit will do logic operations AND, OR, XOR, and XNOR with the aid of the recommended CMOS technology, while the arithmetic unit will do the arithmetic operations addition, subtraction, increment, and buffering operation. The arithmetic unit is constructed using the 4x1 MUX, 2x1 MUX, and full adder, and the 4x1 MUX, required logic gates, and 4x1 MUX are employed to create the logical unit. Using Cadence Virtuoso Gpdk 180nm Technology, the results of the simulation of the 32-bit ALU, the ideal delay, and the Power were calculated.