Bin Yan

Fractional-order modeling provides a flexible framework for extending memristive circuits with memory-dependent dynamics. This work develops a DC-driven memristive chaotic circuit within a unified fractional-order framework. The memristor is formulated with the Caputo derivative and discretized using Sayed’s scheme; the conventional first-order model is recovered at $q=1$, whereas $0<q<1$ introduces nonlocal, history-dependent memory. The system dynamics are systematically analyzed through phase portraits, Lyapunov exponent spectra, bifurcation diagrams, $C_0$ complexity, and the 0–1 test. Quantitative results show that the circuit exhibits a positive maximum Lyapunov exponent over the effective range $q\in [0.78,1]$, with a representative value of ${\mathrm{LE}}_{\max }=0.217$ at $q=0.98$, and an averaged multi-scale $C_0$ complexity of $C_0^{\mathrm{avg}}=0.12$ in the parameter plane. Practical circuit-element bounds are set as $L\in [1,10]\mathrm{H}$, $C\in [0.1,0.14]\mathrm{F}$, and $V_{\mathrm{in}}\in [-5,-2]\mathrm{V}$, while the fractional-capacitor approximation is valid over $f\in [0.01\mathrm{Hz},100\mathrm{Hz}]$ with a magnitude error below $1.5\mathrm{dB}$. These results reveal that the fractional order q acts as a key bifurcation parameter regulating the system’s complexity and stability. To connect theoretical analysis with practical application, a dual-platform simulation framework is developed, utilizing MATLAB/Simulink for algorithmic verification and PSpice for circuit-level validation. An active emulator-based approach is proposed and validated at the circuit-simulation level. Operational amplifiers and analog multipliers are employed to implement the state equations by mapping the state variables to voltage signals. This study establishes a systematic methodology from mathematical modeling to circuit-level verification, emphasizing the significance of fractional-order control and emulation techniques in memristive chaotic systems.