O. Gevin

The SALSA chip will be a versatile ASIC designed for various MPGD applications, including TPCs, trackers, and photon detection. It will feature 64 channels with tunable front-ends and fast ADCs, and a configurable DSP for data correction and feature extraction. The front-end includes a high open loop gain Charge Sensitive Amplifier (CSA), a pole-zero cancellation circuit, and a shaper, with four dynamic ranges and eight peaking times. The ADC is based on a Hybrid RC 12-bit 50 MS/s Successive Approximation Architecture (SAR). The SALSA chip is intended to equip the ePIC MPGD trackers of the Electron Ion Collider (EIC) experiment currently under construction at Brookhaven National Lab (BNL). Several ASIC prototypes have already been designed and tested to validate the main analog building blocks of the future SALSA chip such as analog channel, ADC, PLL, embedded analog and digital probes, I2C and others.

The SALSA chip is a future readout ASIC foreseen for the MPGD detectors, developed in the framework of the EIC collider project, to equip the MPGD trackers of the EPIC experiment. It is designed to be versatile, to be adapted to other usages of MPGD detectors like TPC or photon detectors. It integrates a frontend block and an ADC for each of the 64 channels, associated to a configurable DSP processor meant to correct data and reduce the raw data flux to limit the output bandwidth. It will be compatible with the continuous readout foreseen for the EPIC DAQ, but will also work in a triggered environment. Several prototypes are already produced in order to qualify the different blocks of the chip, in particular the frontend, the ADC and the clock generation. The next 32-channel prototype is currently under development and is planed to be produced in 2025. The final prototype will be produced and tested from 2026 for a production of the SALSA chip at the horizon of 2027.