An Zhong

Most widely deployed ISAs for general-purpose processors expose a centralized register file and instruction-granular control flow, forcing modern CPUs to rely on complex microarchitectural mechanisms to reconcile execution with architectural state. Even in simple in-order designs, these abstractions impose back-and-forth execution overheads, while more aggressive processors further amplify them through register renaming, speculation, and in-order retirement. This letter presents the Block-based Instruction Set Computer (BISC), which rethinks ISA abstractions at block granularity. BISC eliminates architectural destination registers by binding each instruction's result to its position within a block, enabling block-local execution driven by operand availability while preserving control-flow semantics across blocks. Control flow is resolved at block entry, amortizing fetch and control overhead across multiple operations and enabling efficient expression of conditional selection without additional control-flow edges. We evaluate BISC using a single-issue in-order core with comparable area to a RISC-V baseline. Despite executing more operations and incurring a larger code footprint, BISC achieves a 34% geometric mean speedup across benchmarks. These results demonstrate that ISA-level execution abstractions play a critical role in processor efficiency, independent of microarchitectural optimizations.