Martina Baldini

Hydrogenated amorphous silicon (a-Si:H) is a mature thin-film technology for large-area devices and thin-film sensors, and its low-temperature growth via Plasma-Enhanced Chemical Vapor Deposition (PECVD) makes it particularly suitable for biomedical flexible and wearable platforms. However, the reliable integration of a-Si:H sensors on polymer substrates requires a quantitative assessment of their electrical stability under mechanical stress, since bending-induced variations may affect sensor accuracy. In this work, we provide a quantitative, direction-dependent evaluation of the static-bending robustness of both single-doped a-Si:H layers and complete p-i-n junction stacks on polyimide (Kapton^®), thereby linking material-level strain sensitivity to device-level functionality. First, n- and p-doped a-Si:H layers were deposited on 50 µm thick Kapton^® and then structured as two-terminal thin-film resistors to enable resistivity extraction under bending conditions. Electrical measurements were performed on multiple samples, with the current path oriented either parallel (longitudinal) or perpendicular (transverse) to the bending axis, and resistance profiles were determined as a function of bending radius. While n-type layers exhibited limited and mostly gradual variations, p-type layers showed a stronger sensitivity to mechanical stress, with a critical-radius behavior under transverse bending and a more progressive evolution in the longitudinal one. This directional response identifies a practical bending condition under which doped layers, particularly p-type films, are more susceptible to strain-induced degradation. Subsequently, a linear array of a-Si:H p-i-n sensors was fabricated on Kapton^® substrates with two different thicknesses (25 and 50 µm thick) and characterized under identical bending conditions. Despite the increased strain sensitivity observed in the single-layers, the p-i-n diodes preserved their rectifying behavior down to the smallest radius tested. Indeed, across the investigated radii, the reverse current at −0.5 V remained consistent, confirming stable junction operation under bending. Only minor differences, related to substrate thickness, were observed in the reverse current and in the high-injection regime. Overall, these results demonstrate the mechanical robustness of stacked a-Si:H junctions on polyimide and support their use as sensors for wearable biosensing architectures. By establishing a quantitative, orientation-aware stability benchmark under static bending, this study supports the design of reliable a-Si:H flexible sensor platforms for curved and wearable surfaces.

This work presents an advanced electro-physical model for hydrogenated amorphous silicon (a-Si:H) Junction Field Effect Transistors (JFETs) to enable the design of devices with energy-efficient analog interface building blocks for Lab-on-Chip (LoC) systems. The presence of this device can support monolithic integration with thin-film sensors and circuit-level design through a validated compact formulation. The model accurately describes the behavior of a-Si:H JFETs addressing key physical phenomena, such as the channel thickness dependence on the gate-source voltage when the channel approaches full depletion. A comprehensive framework was developed, integrating experimental data and mathematical refinements to ensure robust predictions of JFET performance across operating regimes, including the transition toward full depletion and the associated current-limiting behavior. The model was validated through a broad set of fabricated devices, demonstrating excellent agreement with experimental data in both the linear and saturation regions. Specifically, the validation was carried out at 25 °C on 15 fabricated JFET configurations (12 nominally identical devices per configuration), using the mean characteristics of 9 devices with standard-deviation error bars. In the investigated bias range, the devices operate in a sub-µA regime (up to several hundred nA), which naturally supports µW-level dissipation for low-power interfaces. This work provides a compact, experimentally validated modeling basis for the design and optimization of a-Si:H JFET-based LoC front-end/readout circuits within technology-constrained and energy-efficient operating conditions.