Yanan Luo
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Research Subjects
Research Interests
Yanan Luo has a total of 3 co-authors. Here are the top co-authors by number of shared publications:
- Fei Yang
State Key Laboratory of Media Convergence and Communication, Communication University of China, Beijing 100024, China
2 shared publications - Gang Yang
School of Information and Communication Engineering, Communication University of China, Beijing 100024, China
1 shared publication - Gang Yang
State Key Laboratory of Media Convergence and Communication, Communication University of China, Beijing 100024, China
1 shared publication
Latest Publications
- Open Access
- 6 January 2026
- Published by MDPI AG in Electronics
- Vol. 15 (2) , 252
Optimized DPD Design with Peak-Detection-Based Loop-Delay Estimation for Power Amplifier Linearization: Addressing High–Low Power Distortion via Memory-Clustering Biased Polynomial
This paper proposes an optimized digital predistortion (DPD) framework. Firstly, a peak-detection-based loop-delay estimation is developed by leveraging the unique peak distribution of Orthogonal Frequency Division Multiplexing (OFDM) signals. It reduces the required number of samples to as small as two without compromising estimation accuracy. Then, a Biased Memory Polynomial (BMP) model is proposed for power amplifier modeling. It addresses low-power inaccuracies caused by circuit imperfections (e.g., DC offsets) by adding a bias term to conventional memory polynomials, improving linearization accuracy in low-power regime. Last, to improve the accuracy of coefficient derivation, Memory-Clustering Biased Memory Polynomial (MBMP) is proposed by grouping signals into clusters based on memory-attenuated input vectors and processing them with dedicated sub-models. It improves linearization accuracy in high-power regime. Experimental results demonstrate that the MBMP model reduces normalized mean square error (NMSE) by 16.12 dB, and reduces adjacent channel power ratio (ACPR) by about 12 dBm compared to conventional MP.
- 6 January 2026
- Published by MDPI AG in Electronics
- Vol. 15 (2) , 252
Open AccessOptimized DPD Design with Peak-Detection-Based Loop-Delay Estimation for Power Amplifier Linearization: Addressing High–Low Power Distortion via Memory-Clustering Biased Polynomial
This paper proposes an optimized digital predistortion (DPD) framework. Firstly, a peak-detection-based loop-delay estimation is developed by leveraging the unique peak distribution of Orthogonal Frequency Division Multiplexing (OFDM) signals. It reduces the required number of samples to as small as two without compromising estimation accuracy. Then, a Biased Memory Polynomial (BMP) model is proposed for power amplifier modeling. It addresses low-power inaccuracies caused by circuit imperfections (e.g., DC offsets) by adding a bias term to conventional memory polynomials, improving linearization accuracy in low-power regime. Last, to improve the accuracy of coefficient derivation, Memory-Clustering Biased Memory Polynomial (MBMP) is proposed by grouping signals into clusters based on memory-attenuated input vectors and processing them with dedicated sub-models. It improves linearization accuracy in high-power regime. Experimental results demonstrate that the MBMP model reduces normalized mean square error (NMSE) by 16.12 dB, and reduces adjacent channel power ratio (ACPR) by about 12 dBm compared to conventional MP.
- Open Access
- 4 January 2026
- Published by MDPI AG in Electronics
- Vol. 15 (1) , 228
Symmetrized Extrinsic Information Transfer Chart Analysis for Joint Decoding Between LDPC Codes and CCDMs
This paper proposes a symmetrized extrinsic information transfer (S-EXIT) chart analysis for probabilistic shaped (PS) systems to optimize the joint decoding of low-density parity-check (LDPC) codes and constant composition distribution matchers (CCDMs). A major challenge in analyzing PS systems is the non-uniform channel input caused by shaping, which invalidates the all-zero assumption of traditional EXIT charts, coupled with the three-node structure of the joint decoder (variable nodes, check nodes, and shaping nodes) that exceeds the two-decoder framework of conventional EXIT analysis. To resolve these issues, we first prove the symmetry of the joint decoder and introduce a “symmetrized density” transformation to render the channel output symmetric, thereby enabling the extension of EXIT chart analysis to PS systems. We then approximate the EXIT function of the shaping node decoder via polynomial fitting and integrate it with the variable node decoder into a unified model (VSND) for threshold analysis. On one hand, the proposed S-EXIT chart provides a theoretical threshold for the joint decoder, which is crucial for guiding system design. On the other hand, it enables the joint optimization of LDPC code rates and CCDM rates, unlocking additional performance gains. Simulations over additive white Gaussian noise (AWGN) channels demonstrate that short-blocklength CCDMs (e.g., blocklength 20) achieve up to 1.2 dB gain over uniform systems via S-EXIT-based rate optimization. This work addresses the performance limitations of short-blocklength CCDMs in high-speed optical transmissions, offering a practical and efficient analytical tool for PS system design.
- 4 January 2026
- Published by MDPI AG in Electronics
- Vol. 15 (1) , 228
Open AccessSymmetrized Extrinsic Information Transfer Chart Analysis for Joint Decoding Between LDPC Codes and CCDMs
This paper proposes a symmetrized extrinsic information transfer (S-EXIT) chart analysis for probabilistic shaped (PS) systems to optimize the joint decoding of low-density parity-check (LDPC) codes and constant composition distribution matchers (CCDMs). A major challenge in analyzing PS systems is the non-uniform channel input caused by shaping, which invalidates the all-zero assumption of traditional EXIT charts, coupled with the three-node structure of the joint decoder (variable nodes, check nodes, and shaping nodes) that exceeds the two-decoder framework of conventional EXIT analysis. To resolve these issues, we first prove the symmetry of the joint decoder and introduce a “symmetrized density” transformation to render the channel output symmetric, thereby enabling the extension of EXIT chart analysis to PS systems. We then approximate the EXIT function of the shaping node decoder via polynomial fitting and integrate it with the variable node decoder into a unified model (VSND) for threshold analysis. On one hand, the proposed S-EXIT chart provides a theoretical threshold for the joint decoder, which is crucial for guiding system design. On the other hand, it enables the joint optimization of LDPC code rates and CCDM rates, unlocking additional performance gains. Simulations over additive white Gaussian noise (AWGN) channels demonstrate that short-blocklength CCDMs (e.g., blocklength 20) achieve up to 1.2 dB gain over uniform systems via S-EXIT-based rate optimization. This work addresses the performance limitations of short-blocklength CCDMs in high-speed optical transmissions, offering a practical and efficient analytical tool for PS system design.