Ali Kia

Field-programmable gate arrays (FPGAs) are increasingly used to bring biometric recognition from cloud- or GPU-centric deployments to resource-constrained edge devices where latency, power, and privacy are critical. This paper surveys recent (2021–2025) FPGA and FPGA-SoC implementations across five widely deployed modalities: face, fingerprint, iris, speaker (voiceprint), and finger vein. For each modality, we summarize representative implementations and the performance figures commonly reported in the literature (e.g., accuracy or EER, latency/throughput, resource usage, and power), highlighting the algorithm–hardware co-design choices that enable real-time operation. Across modalities, successful designs repeatedly employ streaming/dataflow architectures, aggressive quantization and fixed-point arithmetic, reuse-aware buffering, and heterogeneous CPU–FPGA partitioning, often supported by high-level synthesis and vendor deep learning IP. Beyond throughput, we discuss how FPGAs facilitate privacy-preserving on-device processing and can integrate template protection and presentation attack detection within the same fabric. Finally, we identify open challenges related to scalability to larger models, memory-bandwidth constraints, and design productivity, and outline research directions enabled by emerging adaptive FPGA architectures and more automated toolflows. Overall, the surveyed evidence indicates that FPGAs are a compelling platform for deterministic, energy-efficient, and secure biometric inference at the sensor edge.

Wearable electrochemical biosensors often producevoltammetric signals that are corrupted by noise and long-term drift.Effective on-device denoising is critical to improve signal quality anddetect anomalies due to sensor drift or interference. This paperexplores lightweight TinyML models for denoising and drift detectionin wearable sensor voltammograms under the strict memoryconstraints of microcontrollers. We apply compact 1D convolutionaland dense autoencoder networks, as well as a PCA-basedreconstruction, to remove noise and identify drifting signals. Using apublic NIST dataset of cyclic voltammograms with added syntheticnoise and artifacts, we evaluate each model’s denoising performance(signal reconstruction MSE) and drift/anomaly detection capability (ROC-AUC) versus its memory footprint (quantized int8 model size). Results show that a small Conv1D autoencoder (8KB weights) canreduce noise by 75% and achieve 0.89 AUC for drift detection,approaching the performance of a larger dense autoencoder (35KB)and outperforming PCA. We observe a trade-off between model sizeand generalization: the larger autoencoder nearly perfectly flaggedanomalies (AUC 1.0) but smaller models remain competitive whileusing 4–6× less memory. These findings demonstrate that drift-resilient signal enhancement can be achieved on-device with minimalresource usage, enabling more robust wearable electrochemicalsensing.

The proliferation of Internet of Things (IoT) devices and embedded processors has recently spurred rapid advances in hardware-level security. This paper systematically reviews developments in securing microcontroller units (MCUs) and constrained embedded platforms from 2020 to 2026, a period marked by the finalization of NIST’s post-quantum cryptography standards and accelerated commercial deployment of hardware security primitives. Through analysis of the peer-reviewed literature, industry implementations, and standardization efforts, we survey five critical areas: post-quantum cryptography (PQC) implementations on resource-constrained hardware, physically unclonable functions (PUFs) for device authentication, hardware Roots of Trust and secure boot mechanisms, side-channel attack mitigations, and Trusted Execution Environments (TEEs) for microcontroller-class devices. For each domain, we analyze technical mechanisms, deployment constraints (power, memory, cost), security guarantees, and commercial maturity. Our review distinguishes itself through its integration perspective, examining how these primitives must be composed to secure real-world embedded systems, and its emphasis on post-standardization PQC developments. We highlight critical gaps including PQC memory overhead challenges, ML-resistant PUF designs, and TEE developer friction, while documenting commercial progress such as PSA Level 3 certified components and 500+ million PUF-enabled devices deployed. This synthesis provides practitioners with practical guidance for securing the next generation of IoT and embedded systems.