Youngmin Jang
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Youngmin Jang has a total of 5 co-authors. Here are the top co-authors by number of shared publications:
- Eunsu Kim
Department of Intelligent Semiconductors, Soongsil University, Seoul 06978, Republic of Korea
1 shared publication - Hyungchul Im
Department of Intelligent Semiconductors, Soongsil University, Seoul 06978, Republic of Korea
1 shared publication - Jonggwon Kim
Department of Intelligent Semiconductors, Soongsil University, Seoul 06978, Republic of Korea
1 shared publication - Semin Kim
Department of Intelligent Semiconductors, Soongsil University, Seoul 06978, Republic of Korea
1 shared publication - Seongsoo Lee
Department of Intelligent Semiconductors, Soongsil University, Seoul 06978, Republic of Korea
1 shared publication
Latest Publications
- Open Access
- 14 May 2026
- Published by MDPI AG in Electronics
- Vol. 15 (10) , 2108
Hardware–Software Co-Optimized Lightweight Real-Time CAN Intrusion Detection and Prevention System for ECUs
The Controller Area Network (CAN) protocol used in in-vehicle networks is vulnerable to external attacks because it lacks authentication and encryption mechanisms. Accordingly, CAN Intrusion Detection Systems (IDSs) have been studied. However, existing IDSs remain difficult to deploy in practical vehicles because of their limited real-time capability, complex preprocessing, and high computational cost. To overcome these limitations, this paper proposes an ultra-lightweight Convolutional Neural Network (CNN)-based IDS that significantly reduces parameters and computational complexity while maintaining high detection performance. The proposed IDS improves area efficiency through a streaming pipeline, computation-block reuse, and constrained Processing Element (PE) parallelism. In addition, its lightweighting effect was quantitatively evaluated against an RTL baseline implemented under identical platform and design constraints. When an attack is detected, an Intrusion Prevention System (IPS) integrated with the CAN controller generates an error frame to block it in real time. The proposed IDS achieved over 99.97% detection performance for known frame-level message-injection scenarios on the Car-Hacking Dataset. It also achieved branch-wise real-time feasibility with an 11.46 µs ID-branch precomputation latency and a 5.68 µs DATA-complete-to-decision latency at 50 MHz. In TSMC 28 nm ASIC synthesis, the proposed IDS required 70,592 gates, with an estimated ASIC power of 2.0231 mW and an active inference energy of 34.68 nJ.
- 14 May 2026
- Published by MDPI AG in Electronics
- Vol. 15 (10) , 2108
Open AccessHardware–Software Co-Optimized Lightweight Real-Time CAN Intrusion Detection and Prevention System for ECUs
The Controller Area Network (CAN) protocol used in in-vehicle networks is vulnerable to external attacks because it lacks authentication and encryption mechanisms. Accordingly, CAN Intrusion Detection Systems (IDSs) have been studied. However, existing IDSs remain difficult to deploy in practical vehicles because of their limited real-time capability, complex preprocessing, and high computational cost. To overcome these limitations, this paper proposes an ultra-lightweight Convolutional Neural Network (CNN)-based IDS that significantly reduces parameters and computational complexity while maintaining high detection performance. The proposed IDS improves area efficiency through a streaming pipeline, computation-block reuse, and constrained Processing Element (PE) parallelism. In addition, its lightweighting effect was quantitatively evaluated against an RTL baseline implemented under identical platform and design constraints. When an attack is detected, an Intrusion Prevention System (IPS) integrated with the CAN controller generates an error frame to block it in real time. The proposed IDS achieved over 99.97% detection performance for known frame-level message-injection scenarios on the Car-Hacking Dataset. It also achieved branch-wise real-time feasibility with an 11.46 µs ID-branch precomputation latency and a 5.68 µs DATA-complete-to-decision latency at 50 MHz. In TSMC 28 nm ASIC synthesis, the proposed IDS required 70,592 gates, with an estimated ASIC power of 2.0231 mW and an active inference energy of 34.68 nJ.