Multi-Pulse Si-MOSFET Gate Driving Utilizing Gate Loop Inductance

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Abstract
Gate driving circuits are a crucial part of the safety, compliance, and performance of switched-mode power converters. Traditionally, these circuits use a single pulse and employ a gate resistor to control silicon (Si) MOSFETs. Unfortunately, the performance of this approach is limited by parasitic inductances, which can cause excessive oscillations, voltage stress, and catastrophic false turn-ON failures. As a result, power conversion applications typically sacrifice performance with respect to increased transient times and switching losses to maintain safe operation. This work proposes a simple multi-pulse (MP) driving sequence that enables reduced transient times and switching losses while keeping oscillations and voltage stress low. With this, the performance can be increased while upholding safety margins of the switched-mode power converter. The concepts and derived equations are verified by circuit simulations and experiments showcasing up to 25% loss reduction in the driver-stage, up to. 2% efficiency improvement in the power-stage, and up to 18X oscillation amplitude reduction compared to the conventional approach. Moreover, the proposed sequence and driving circuit achieve reliable operation in extreme slew-rate conditions beyond the capabilities of the traditional approach, resulting in voltage stress reduction and false turn-ON failure mitigation.

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