Implementing Register Files for High-Performance Microprocessors in a Die-Stacked (3D) Technology
Authors:
- K. PuttaswamyKPK. Puttaswamy
- G.H. LohGLG.H. Loh
- 10 March 2006
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 00, 384-392
Abstract
No abstract availableThis publication has 18 references indexed in Scilit:
- Implementing caches in a 3D technology for high performance processors2006
- Reducing the complexity of the register file in dynamic superscalar processors2005
- Design aspects of a microprocessor data cache using 3D die interconnect technology2005
- 2.5D system integration: a design driven system implementation schema2004
- Technology, performance, and computer-aided design of three-dimensional integrated circuits2004
- Fabrication technologies for three-dimensional integrated circuits2003
- 3D direct vertical interconnect microprocessors test vehicle2003
- Banked multiported register files for high-frequency superscalar microprocessors2003
- New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation2002
- The Alpha 21264 microprocessorIEEE Micro, 1999