Design Space Exploration of DVFS on On-Chip Hybrid Communication Networks

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Abstract
Multi-Processor Systems-on-Chip (MPSoCs) have been established as the standard platform for high-performance applications in the semiconductor industry. With an increasing number of Processing Elements (PEs) in a single die, communication scalability is one of the foremost concerns. Networks-on-Chip (NoCs) has already shown to be an alternative to provide scalability, but relies on homogeneous communication fashion which cannot be ideal to heterogeneous communication demand of current embedded devices. Hybrid communication structures can mitigate such issues by merging different communication structures that can better accommodate heterogeneous communication rates. In this work, an Hybrid Communication Infrastructure is proposed by merging fully- partially- and peer to peer connected fabrics providing a wide range of communication bandwidth. In addition, we coupled to the hybrid fabric, a multi-grained DVFS approach that dynamically adapts voltage and frequency of the structures considering the application's performance needs. Results shows that the Hybrid structure achieves up to 22% power savings and occupied 42% less chip area than a NoC with the same number of PEs. Experiments with relevant video encoding applications show power savings of up to 70% over a homogeneous NoC, with no significant throughput losses, both coupled to the proposed DVFS approach.

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