GAAFET Versus Pragmatic FinFET at the 5nm Si-Based CMOS Technology Node
Open Access
- 30 March 2017
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of the Electron Devices Society
- Vol. 5 (3) , 164-169
Abstract
Speed and power performances of Si-based stacked-nanowire gate-all-around (GAA) FETs and pragmatic ultra-thin-fin FETs at the 5nm CMOS technology node are projected, compared, and physically explained based on 3-D numerical simulations. The respective device domains are also used to compare integration densities based on 6T-SRAM layouts. Predicted comparable performances and densities, with considerations of the complexity/cost of GAAFET processing versus that of the FinFET with pragmatic simplifications, suggest that the FinFET is the better choice for the future.Keywords
Funding Information
- Ministry of Science and Technology, Taiwan
- National Center for High-performance Computing
- National Nano Device Laboratories
- National Chip Implementation Center
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