An Inverter-Based Sampling Front-End Achieving >46-dB SFDR at 50-GHz Input
- 18 March 2025
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Solid-State Circuits Letters
- Vol. 8, 81-84
Abstract
This letter presents a 32-GS/s per-way hierarchical sampling front-end (SFE) for time-interleaved ADCs, featuring both high linearity and energy efficiency with inherent embedded gain from an inverter-based topology. The P/N ratio configuration extends its applicable input common-mode voltage range. Both active and passive extensions improve the bandwidth of the SFE supplied by a core-device voltage. Furthermore, an improved dual-path bootstrapped switch enhances the sampling bandwidth and linearity at 8 GS/s. Fabricated in a 28-nm CMOS process, the inverter-based SFE achieves 30-GHz bandwidth while consuming 49.4 mW from a 0.95-V supply. The measured spurious free dynamic range (SFDR) and signal-to-noise and -distortion ratio (SNDR) at 50-GHz input are 46.9 dB and 36.1 dB, respectively.Keywords
Funding Information
- Macau Science and Technology Development Fund (0129/2024/AMJ, 0137/2024/RIB2)
- University of Macau Research (MYRG-GRG2024-00257-IME)
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