Yan Zhu

This article presents a 72-GS/s 9-bit time-interleaved (TI) pipeline-successive approximation register successive approximation register (SAR) analog-to-digital converter (ADC) that achieves a spurious-free dynamic range (SFDR) of over 55 dB at a 20-GHz input. The design features a hierarchical interleaver in conjunction with common-source-compensated source-follower buffers and fully split bootstrap switches. They enhance both the bandwidth and linearity of the TI-ADC for high-frequency (HF) inputs while alleviating bandwidth mismatches across channels. A resistor-over-resistor (R/R)-based residue amplifier (RA) and a common-mode voltage ( $V_{\mathbf {CM}}$ )-regulated switching scheme stabilize the inter-stage gain (ISG) in the unit pipeline-SAR ADC. The 72-GS/s prototype is fabricated using a 16-nm FinFET process and consumes 393.6mW, excluding an off-chip TI mismatch calibration engine. It achieves a 46.4-dB signal-to-noise-and-distortion ratio (SNDR) and a 63.6-dB SFDR at a low-frequency (LF) input, while a 37.0-dB SNDR and 49.3-dB SFDR at a Nyquist input.

This article presents a single-channel successive approximation register (SAR)-assisted fourth-order noise-shaping (NS) pipeline analog-to-digital converter (ADC) with residue amplifier (RA) error shaping. The first stage introduces a passive dynamic range (DR)-preserved feedforward (FF) NS, which shapes both the quantization error and various impairments from the RA, thus enabling a fast, low power, and voltage-and-temperature (VT) variation robust amplification. Further incorporating a coarse NS-SAR ADC to speed up the first-stage conversion, the critical path, formed by the quantization and amplification in the pipeline ADC, can be considerably shrunk, thus allowing for a high sampling rate. The second stage shares the error-shaped RA to achieve a second-order error feedback (EF) NS with optimized zeros, and simultaneously nests a simply passive first-order FF NS. These overall aggregate an aggressive fourth-order NS, achieving the desired SQNR under a low oversampling ratio (OSR), facilitating a low-power wideband design. Fabricated in 28-nm CMOS, the ADC prototype runs at a 760 MHz sampling rate and retains 100 MHz bandwidth (BW) with a signal-to-noise-and-distortion ratio (SNDR) of 70.15 dB under a small OSR of 3.8. It consumes 4.52 mW of power at a 1 V supply, yielding a Schreier figure-of-merit (FoM) of 173.6 dB. With a one-time-only trimming, the SNDR varies by 2 and 2.5 dB across a supply variation of ±10% and a temperature range of $- 20~^{\circ }$ C to $70~^{\circ }$ C, respectively.

This article presents a noise-shaping time-domain analog-to-digital converter (NS TD-ADC)-assisted continuous/discrete time (C/DT) hybrid pipelined ADC architecture in conjunction with a single operational transconductance amplifier (OTA) second-order residue amplifying filter (RAF), facilitating high power efficiency at wideband target. Besides, using a high-speed NS TD-ADC as the 1st-stage sub-quantizer (QTZ) effectively suppresses the tonal behavior due to the low-resolution residue. The RAF exploits the single-amplifier biquad (SAB)-based structure to realize a single OTA second-order filtering, thus simplifying the design and preserving high energy efficiency. The backend DT QTZ is with $2{\times }$ time-interleaved (TI), which eases the compromise between speed and power efficiency in the CT pipelined (CT Pipe) ADC design. Fabricated in a 28-nm process, the design obtains 65.4-dB signal-to-noise and distortion ratio (SNDR) with 320-MHz bandwidth while consuming 56.17 mW from 1.4- to 0.95-V power supplies. The prototype exhibits a dynamic range of 68 dB with a Schreier figure of merit (FoM) of 163 dB, demonstrating a high power efficiency under 2.4-GHz sampling frequency.

This article presents a reservoir-charge-redistributed (RCR) successive approximation register (SAR) analog-to-digital converter (ADC) that facilitates a high linearity and compact area in low power. Conventional on-chip passive charge sharing (PCS) mitigates the bondwire influence on the off-chip reference voltage for the capacitive digital-to-analog converter (DAC) ( $C_{\text {DAC}}$ ). It, however, suffers from a considerable reservoir capacitor ( $C_{\text {REF}}$ ), poor linearity, and dynamic range (DR) loss. Unlike prior PCS schemes, the proposed RCR offers an individual $C_{\text {REF}}$ to each bit trial, and each $C_{\text {REF}}$ only performs charge redistribution once, which is enabled by the subranging architecture. These unique characteristics significantly decouple the compromise between linearity and DR loss and area. Furthermore, a configurable sequentially charged floating inverter amplifier (SC-FIA)-based comparator is also presented to improve energy efficiency further. Incorporated these techniques in a 16-bit SAR ADC, the prototype in 65-nm CMOS process achieves an 80.9-dB signal-to-noise-and-distortion ratio (SNDR) and 100.3-dB spurious-free dynamic range (SFDR) at Nyquist input, consuming $291.7~\mu $ W power from a single supply at 1 MS/s, and yielding a 32.1-fJ/conv.-step Walden figure of merit (FoM_W) and 173.3-dB Schreier FoM (FoM_S).

This paper presents a lightweight background calibration for the distortion of the analog-to-digital converter (ADC)’s input buffer. The buffer’s nonlinearity is calibrated on-chip by the Harmonic-Compensated Diode Load (HC-DL), whose bias voltage is determined by the calibration algorithm facilitated by dither injection at the input of the buffer. A two-step ADC is exploited to demonstrate the calibration, where the coarse-fine ADC gain mismatch and sampling skew at the $1^{\mathbf {st}}$ step are calibrated by monitoring the occupation of the correction range (OCR) at the $2^{\mathbf {nd}}$ step. Verified in a 12b 1 GS/s pipe-SAR ADC in 28 nm CMOS, the SNDR and SFDR at Nyquist input are 60.96 dB/76.8 dB, respectively and the SFDR keeps >75 dB over PVT.

This letter presents a 32-GS/s per-way hierarchical sampling front-end (SFE) for time-interleaved ADCs, featuring both high linearity and energy efficiency with inherent embedded gain from an inverter-based topology. The P/N ratio configuration extends its applicable input common-mode voltage range. Both active and passive extensions improve the bandwidth of the SFE supplied by a core-device voltage. Furthermore, an improved dual-path bootstrapped switch enhances the sampling bandwidth and linearity at 8 GS/s. Fabricated in a 28-nm CMOS process, the inverter-based SFE achieves 30-GHz bandwidth while consuming 49.4 mW from a 0.95-V supply. The measured spurious free dynamic range (SFDR) and signal-to-noise and -distortion ratio (SNDR) at 50-GHz input are 46.9 dB and 36.1 dB, respectively.

This work presents an always-on CNN processor featuring compute-in-memory (CIM) and layer-fusion (LF) techniques. It demonstrates an end-to-end neural network (NN) inference while eliminating memory accesses for both the weight and inter-layer activation, thus significantly saving associated energy. The analog LF-CIM processor combines charge-and time-domain multiply-accumulate (MAC) arrays in a fusional manner, avoiding the need for the interfacial analog-to-digital and digital-to-analog converters; it also supports a highly sparsity-adaptive network and exhibits low-voltage-supplied tolerance to circuit noise and variations, which facilitates an energy-efficient and robust CNN processor, simultaneously. Furthermore, the full-precision activation originating from the LF reduces the NN parameters and operations, while the inference accuracy is improved by the presented ensemble NN. The prototype processor is fabricated in a 28-nm CMOS process, demonstrating a fully on-chip MNIST inference with 97.9% accuracy. It operates at 3,508 frames per second while consuming 11.6 μW at a 0.5-V supply; the achieved efficiency of 3.32 nJ/frame is over 50-fold than the state-of-the-art end-to-end MNIST accelerators.

This article presents a single-channel 10-bit pipelined analog-to-digital converter (ADC) with a dual-path time-assisted residue generation (TARG) technique running at 2.6 GS/s. A voltage-to-time converter (VTC) driving a current-integrating capacitor array through a time pulse facilitates the inter-stage residue amplification, which decouples the constraint between linearity and speed of the residue generation. The time residue path shortens the residue generation period with a lower linearity requirement and quantizes 4 bits simultaneously, speeding up the sub-stage ADC conversion; the voltage residue path achieves a dedicated inter-stage gain with high linearity and relaxed timing, suppressing noise of its subsequent stages. Furthermore, the inherent complementation characteristic of the voltage–time–voltage (V–T–V) conversion in the TARG scheme makes the prototype ADC intrinsically robust to process, voltage, and temperature (PVT) variations. Fabricated in a 28-nm CMOS process, the 2.6-GS/s pipelined ADC achieves a 51.4-dB signal-to-noise and distortion ratio (SNDR) and a 71.0-dB spurious-free dynamic range (SFDR) with a Nyquist input at a 0.9-V power supply, exhibiting a Walden figure-of-merit of 17.6 fJ/conversion-step. The SNDR varies by 1.25 and 1.55 dB across a supply variation of $\pm$ 5% and a temperature range of $-$ 40 $^{\circ}$ C to 85 $^{\circ}$ C, respectively.

This article presents a 12-GS/s 12-bit 4 $\times$ time-interleaved (TI) pipelined analog-to-digital converter (ADC), which utilizes a global dither injection (GDI) scheme to facilitate an input-independent background timing skew calibration. The GDI scheme adds dithers into the input signal of the push–pull source follower (PP-SF) in the input buffer (IBF), avoiding undetectable skews in conventional local dither injection (LDI) schemes. Meanwhile, the perturbations between the input signal and dither are mitigated by cross-coupled capacitive networks. This work also significantly improves the efficiency of the interleaver using the following techniques: first, the PP-SF-based IBF is linearized by a self-adaptive current compensation (SACC), achieving high linearity under 1.2-V low supply voltage headroom. Second, the speed of the 12-bit channel is lifted to 3 GS/s in 28-nm CMOS using a sturdy ring amplifier (SRingAmp) with feedforward (FF), which enables a nonhierarchical interleaver with a small interleaving factor of 4 $\times$ . The time-interleaved ADC attains a 54.1-dB SNDR and a 66.0-dB SFDR under a near-Nyquist input with 179.8-mW power consumption, translating into a Walden figure of merit (FoM) of 36.2 fJ/conversion step and a Schreier FoM of 159.3 dB.

This letter presents a reconfigurable floating-point compute-in-memory (FP-CIM) macro that pre-processes the exponent in the analog domain, enhancing the energy efficiency of edge devices for the FP inference. The presented FP-CIM macro supports FP8 inference, while can be configured to BP16 precision in a segmented computation manner. Furthermore, a time-domain analog-to-digital converter facilitates the analog CIM macro while improving energy efficiency by sharing the counter and quantizing in a coarse-fine structure. Fabricated in a 28-nm CMOS process, the presented FP-CIM macro achieves 314.6-TFLOPS/W energy efficiency and 12.13-TFLOPS/mm2 area efficiency at the FP8 mode.