Spatially Complementary In‐Plane Lattice Strain Engineering for Reduced Contact Resistance and Enhanced Ferroelectric Switching in Van Der Waals α‐In 2 Se 3 Ferroelectric Semiconductor Field‐Effect Transistors

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Abstract
α‐In 2 Se 3 ferroelectric semiconductor field‐effect transistors (FeS‐FETs) offer attractive non‐volatile memory characteristics but are limited by high source/drain (S/D) contact resistance and inefficient ferroelectric polarization switching. Here, we demonstrate a low‐temperature, CMOS‐compatible strain‐engineering strategy based on region‐dependent in‐plane (IP) lattice strain. A silicon nitride stress layer induces tensile strain in the S/D regions and compressive strain in the channel, producing spatially differentiated effects within a single device. The contact‐side tensile strain modifies the interfacial electronic structure and reduces contact resistance, whereas the channel‐side compressive strain facilitates ferroelectric polarization switching. Consequently, the strained α‐In 2 Se 3 FeS‐FET achieves a 12.03‐fold reduction in S/D contact resistance, a 19.21‐fold increase in on‐state current, a 4.4%p increase in normalized memory window, and a 22.4‐fold enhancement in the ferroelectric resistance switching ratio. Raman characterization and finite‐element method simulations establish the region‐dependent strain distribution, while interface‐pinning analysis and first‐principles calculations provide mechanistic support for the distinct contact‐ and channel‐side effects. These results establish region‐dependent IP lattice strain as a unified device‐engineering framework for jointly controlling contact transport and ferroelectric memory functionality in vdW α‐In 2 Se 3 FeS‐FETs.
Funding Information
  • National Research Foundation of Korea (RS‐2025‐00556718)
  • National Research Foundation of Korea (RS‐2025‐25398164)

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