Hyun-Yong Yu

Electrochemical-metallization (ECM) memristors can implement both nonvolatile memory switching and volatile threshold switching, making them attractive for neuromorphic and reservoir computing; however, the stochastic formation of metallic filaments causes variability in the threshold voltage and switching instability. Here, we report a van der Waals α-In2Se3-based ferroelectric-semiconductor ECM (FeS-ECM) memristor in which a bidirectionally polarized α-In2Se3 layer is inserted between the inert electrode and the switching layer. The out-of-plane ferroelectric polarization, programmed through a decoupled in-plane poling terminal, deterministically selects within the low-compliance operating regime between nonvolatile bipolar memory switching and volatile unipolar threshold switching within a single device, with a coefficient of variation in the set voltage of 4.7% and stable operation over more than 9000 cycles. Exploiting these two modes, a single α-In2Se3 platform exhibits both the volatile reservoir dynamics and the nonvolatile conductance modulation required for the readout weights of a physical reservoir-computing system, in which the pulse width electrically programs multiple relaxation time constants. This pulse-width multitime scale reconfigurability enables efficient temporal information processing, demonstrated through MNIST classification and chaotic time-series prediction.

α‐In ₂ Se ₃ ferroelectric semiconductor field‐effect transistors (FeS‐FETs) offer attractive non‐volatile memory characteristics but are limited by high source/drain (S/D) contact resistance and inefficient ferroelectric polarization switching. Here, we demonstrate a low‐temperature, CMOS‐compatible strain‐engineering strategy based on region‐dependent in‐plane (IP) lattice strain. A silicon nitride stress layer induces tensile strain in the S/D regions and compressive strain in the channel, producing spatially differentiated effects within a single device. The contact‐side tensile strain modifies the interfacial electronic structure and reduces contact resistance, whereas the channel‐side compressive strain facilitates ferroelectric polarization switching. Consequently, the strained α‐In ₂ Se ₃ FeS‐FET achieves a 12.03‐fold reduction in S/D contact resistance, a 19.21‐fold increase in on‐state current, a 4.4%p increase in normalized memory window, and a 22.4‐fold enhancement in the ferroelectric resistance switching ratio. Raman characterization and finite‐element method simulations establish the region‐dependent strain distribution, while interface‐pinning analysis and first‐principles calculations provide mechanistic support for the distinct contact‐ and channel‐side effects. These results establish region‐dependent IP lattice strain as a unified device‐engineering framework for jointly controlling contact transport and ferroelectric memory functionality in vdW α‐In ₂ Se ₃ FeS‐FETs.

As CMOS technologies scale, contact resistance at metal/semiconductor interfaces, particularly silicide/Si, has become a key performance limiter. Although silicide/Si generally exhibits low Schottky barrier heights (SBHs) and weak Fermi-level pinning (FLP), vacancy-type defects can substantially alter interfacial electronic properties. Here, density functional theory (DFT) calculations are performed on silicide/Si interfaces, comparing an ideal interface with three single-vacancy configurations: a metal vacancy in the silicide, a Si vacancy in the silicide, and a Si vacancy in the Si region near the interface. A dilute-defect limit is considered by introducing one vacancy per lateral interface area of the supercell (≈0.0052 Å–2). The results show that FLP is governed primarily by defect location. Vacancies within the silicide suppress interfacial charge redistribution and weaken MIGS-like characteristics, leading to reduced pinning and higher pinning factors (S ≈ 0.51–0.52). In contrast, a Si vacancy on the semiconductor side perturbs near-interface electrostatics and enhances LDOS tails in the Si bandgap, resulting in stronger pinning (S ≈ 0.14). This vacancy-induced modulation of FLP directly translates into systematic shifts in SBHs, providing atomistic insight into defect-mediated FLP in silicide/Si interfaces.

A metal–TMO interlayer–semiconductor (MTIS) contact using a sputtered MoO _X interlayer achieves ultra-low contact resistivity, significantly boosting the performance of p-type SnO TFTs.

Computing-in-memory (CIM), which integrates memory for storing neural network weights with in-memory processing units, is a promising artificial intelligence (AI) accelerator owing to its high density and energy efficiency. In CIM design, interdependent device and circuit parameters significantly impact overall performance and expand the design space, requiring novel optimization methodologies to achieve high energy efficiency and throughput. In this paper, we present a surrogate-assisted design technology co-optimization (DTCO) framework that jointly considers device- and circuit-level parameters, such as device dimensions, voltage levels, and clock frequency to maximize CIM performance. The proposed data-driven optimization framework integrates electronic design automation (EDA) tools, machine learning, the strength Pareto evolutionary algorithm, and a robustness score to efficiently explore a high-dimensional objective space with complex trade-offs while reducing computational cost. Optimal design parameters are identified using a robustness-scoring method that evaluates both performance and resilience to process variation, after which an inverse-design approach is applied to implement the CIM macro. The framework demonstrates high predictive accuracy, with mean off-grid normalized errors below 5% across all four objectives. By applying inverse design with the optimized parameters, our CIM macro achieves an energy efficiency of 10361 TOPS/W and a throughput of 12.05 TOPS in simulation, along with 89.08% accuracy on the CIFAR-10 dataset. This DTCO approach effectively addresses complex semiconductor design problems by co-optimizing device and circuit parameters and is extendable to other design challenges.

Complementary field-effect transistors (CFETs) improve integration density through vertical stacking, but dense middle-of-line (MOL) routing introduces significant parasitics that affect circuit performance. This work presents an MOL-aware compact modeling framework for 3-nm CFETs, where MOL-related capacitances are analytically captured using conformal mapping and calibrated with TCAD extraction. The resulting compact model is implemented in a customized PDK based on the BSIM-CMG formulation and supports layout-aware circuit evaluation. Including MOL parasitics increases the total parasitic capacitance by approximately 20%. Post-layout analysis of a 5-stage ring oscillator shows that the MOL contribution to frequency behavior grows with fan-out, while capacitance analysis indicates that the MOL domain accounts for more than half of the total parasitics in low-fan-out conditions. These results demonstrate that MOL effects form a major performance bottleneck in vertically stacked CFETs and highlight the importance of MOL-aware modeling for accurate circuit prediction and design optimization in advanced technology nodes.

The ferroelectric semiconductor field‐effect transistors (FeS‐FETs) based on α‐In ₂ Se ₃ emerge as promising non‐volatile memory devices. However, the intrinsic in‐plane (IP) crystallographic anisotropy of α‐In ₂ Se ₃ introduces orientation dependence, leading to pronounced variations in memory performance depending on the IP alignment of the source/drain (S/D) contacts. This study presents the first demonstration of IP anisotropy‐dependent ferroelectricity in α‐In ₂ Se ₃ FeS‐FETs with S/D contacts aligned along the armchair (AC) and zigzag (ZZ) directions. The AC‐aligned S/D configuration achieves a ferroelectric resistance switching (FRS) ratio of 6.42, an on/off current ratio of 4.53 × 10 ⁴ , and a normalized memory window (MW) of 59 %, whereas the ZZ‐aligned counterpart exhibits an FRS ratio of 1.05, an on/off ratio of 5.25, and negligible MW. The electron transports proceed through twisted pathways along the AC direction, but proceed along a straight trajectory in the ZZ direction to avoid high‐energy barrier regions due to the threefold rotational symmetric lattice. Thus, the excessive electron transmission and a reduced Schottky barrier height effectively screen the influence of ferroelectric bound charges in the ZZ‐aligned S/D contacts. These findings establish clear correlations between IP anisotropy and the ferroelectric functionality of α‐In ₂ Se ₃ , offering critical guidelines for the design of FeS‐FETs.

As semiconductor devices continue to scale, backside power delivery networks (BSPDNs) have emerged as a promising alternative to conventional front-side power delivery networks (FSPDNs), offering improved routing flexibility and power integrity. However, BSPDN integration introduces significant thermo-mechanical challenges, particularly wafer warpage induced by material and structural asymmetry. In this study, wafer warpage evolution during key BSPDN fabrication steps is investigated using calibrated three-dimensional finite element method (FEM) simulations. Warpage increases progressively throughout processing, reaching a convex value of +448.55 lm after high-pressure annealing (HPA), identified as the most critical stage driving final deformation. Analysis of Cu crystal orientations (100, 110, 111) shows only minor variations in warpage, whereas BSPDN Cu interconnection density has a more pronounced influence. Increasing Cu density amplifies thermal expansion mismatch in the backside stack, leading to greater stress accumulation during heating; during HPA, the warpage changes by about 7.41% as Cu interconnection density increases from 40% to 90%. Comparison between FEM results and analytical predictions from Suhirs model shows close agreement, validating the mechanical interpretation. These findings provide a predictive framework for understanding BSPDN-related warpage and offer guidance for layout and process optimization in advanced packaging.