7.4 Gb/s 6.8 mW Source Synchronous Receiver in 65 nm CMOS
- 23 May 2011
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 46 (6) , 1337-1348
Abstract
A high-frequency jitter tolerant receiver in 65 nm CMOS is presented. Jitter tolerance is improved by tracking correlated jitter using a pulsed clock forwarded from the transmitter side. The clock receiver comprises two injection locked oscillators to frequency-multiply, deskew, and adjust jitter tracking bandwidth. Different data rates and latency mismatch between the clock and data paths are accommodated by a jitter tracking bandwidth that is controllable up to 300 MHz. Each receiver consumes 0.92 pJ/bit operating at 7.4 Gb/s and has a jitter tolerance of 1.5 UI at 200 MHz.Keywords
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