A Universal Accelerated Coprocessor for Object Detection Based on RISC-V

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Abstract
With the application of object detection (OD) technology in various fields, common OD methods have been increasingly widely used, which poses a challenge to their calculative performance and accuracy. To improve the computational performance of OD algorithms, a general-purpose accelerated coprocessor was designed and implemented based on the extensibility of the RISC-V architecture. The accelerator was transformed into the form of a coprocessor and connected to its CPU core through the EAI coprocessor interface. Meanwhile, the corresponding instructions were designed, and the acceleration library functions were established. Finally, the performance and resource depletion of the coprocessor were analyzed on the FPGA platform. The experimental results suggest that only 10,091 LUTs were consumed by the accelerated coprocessor designed in this study, accounting for 52.2% of the entire SoC system. Moreover, the processing capacity of the YOLOv3 algorithm was 6.33 times that of a general-purpose CPU.
Funding Information
  • National Natural Science Foundation of China (62201375)
  • China Postdoctoral Science Foundation (2021M691848)
  • Science and Technology Projects Fund of Suzhou (SYG202142)

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