Charge-mode parallel architecture for matrix-vector multiplication
Authors:
- 11 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
An internally analog, extedy digital architec- ture for matrix-vector multiplication is presented. Fully paral- lel processing allows for high data throughput and minimal la- tency. The analog architecture incorporates an array of charge- mode analog computational cells with dynamic storage and mw- parallel fiash analog-to-digital converters (ADC). Each of the cells includes a dynamic storage element and a charge injection de- vice computing binary inner product of two arguments. The ma- trix elements are stored in the array of computational cells in bit-parallel fashion, and the input vector is presented bit-serially. Digital post-processing is then performed on the ADC outputs to construct the resulting product with precision higher than that of each conversion. The analog architecture is tailored for high- density and low power VLSI implementation, and matrix dimen- sions of 128 x 512 and ADC resolution of 6 bits for an overall resolution in excess of 8 bits are feasible on a 3 mm x 3 mm chip in standard CMOS 0.5 pm technology.Keywords
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