SiGe BiCMOS Technology with 3.0 ps Gate Delay

Authors:

1 December 2007

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 651-654
DOI:10.1109/iedm.2007.4419028

Abstract

This work reports on a 130 nm BiCMOS technology with high-speed SiGe:C HBTs featuring a transit frequency of 255 GHz and a maximum oscillation frequency of 315 GHz at an emitter area of 0.17 x 0.53 mum². A minimum gate delay of 3.0 ps was achieved for CML ring oscillators. Breakdown voltages of the HBTs are measured to be BV_CEO=1.8 V, BV_CBO=5.6 V, andBV_EBO=1.9 V.

Keywords

SILICON GERMANIUM
GERMANIUM SILICON ALLOYS
BICMOS INTEGRATED CIRCUITS
DELAY
HETEROJUNCTION BIPOLAR TRANSISTORS
FREQUENCY
CMOS TECHNOLOGY
MILLIMETER WAVE TECHNOLOGY
CMOS PROCESS
RING OSCILLATORS

This publication has 4 references indexed in Scilit:

3.3 ps SiGe bipolar technology
2005
A low-parasitic collector construction for high-speed SiGe:C HBTs
2005
SiGe:C BiCMOS technology with 3.6 ps gate delay
2004
3.21 ps ECL gate using InP/InGaAs DHBT technology
Electronics Letters, 2003