Andreas Mai
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Andreas Mai has a total of 345 co-authors. Here are the top co-authors by number of shared publications:
- Patrick Steglich
Technical Univ. of Applied Sciences Wildau (Germany)
17 shared publications Marco Lisker
IHP-Leibniz-Institut für Innovative Mikroelektronik , Im Technologiepark 25 , 15236 Frankfurt (Oder) , Germany
11 shared publicationsMehmet Kaynak
Department Technology for Smart Systems, Leibniz-Institut fr innovative Mikroelektronik (IHP), Frankfurt (Oder), Germany
11 shared publicationsChristian Mai
IHP - Leibniz-Institut für innovative Mikroelektronik
9 shared publicationsD. Wolansky
IHP, Technol Pk 25, D-15236 Frankfurt, Oder, Germany
9 shared publicationsLars Zimmermann
IHP, Im Technologiepark 25, 15236 Frankfurt (Oder), Germany
9 shared publications
Latest Publications
- Open Access
- 15 October 2026
- Published by Wiley in Advanced Materials Technologies
- p. e71408
Vertical Gate‐All‐Around SiGeSn/GeSn/SiGeSn Nanowire Transistors for Energy‐Efficient Electronics
Conventional Si Complementary Metal Oxide Semiconductor (CMOS) technologies face increasing challenges in improving energy efficiency while maintaining device performance. Here, SiGeSn/GeSn heterostructures are employed as a unified Group‐IV platform for complementary vertical nanowire gate‐all‐around (GAA) MOSFETs and tunnel field‐effect transistors (TFETs) fabricated on Si wafers. The wider‐bandgap SiGeSn source/drain regions introduce band offsets to the GeSn channel, enabling heterostructure band engineering for leakage suppression and tunneling‐pathway control. Compared with all‐GeSn reference devices, the SiGeSn source/drain architecture suppresses drain‐induced barrier lowering and off‐state leakage without modifying the GeSn channel. The same heterostructure platform also enables complementary TFET operation, where the n‐TFET exhibits a subthreshold swing of 60 mV dec − 1 and a two‐order‐of‐magnitude enhancement in on/off current ratio. The performance difference between p‐ and n‐TFETs provides experimental evidence of the different efficiencies of indirect Γ‐to‐L and direct Γ‐to‐Γ tunneling processes. These results demonstrate that SiGeSn/GeSn heterostructures can be used to suppress leakage currents and engineer tunneling pathways, establishing SiGeSn/GeSn heterostructures as a unified Group‐IV platform for future energy‐efficient CMOS technologies beyond conventional Si.
- 15 October 2026
- Published by Wiley in Advanced Materials Technologies
- p. e71408
Open AccessVertical Gate‐All‐Around SiGeSn/GeSn/SiGeSn Nanowire Transistors for Energy‐Efficient Electronics
Conventional Si Complementary Metal Oxide Semiconductor (CMOS) technologies face increasing challenges in improving energy efficiency while maintaining device performance. Here, SiGeSn/GeSn heterostructures are employed as a unified Group‐IV platform for complementary vertical nanowire gate‐all‐around (GAA) MOSFETs and tunnel field‐effect transistors (TFETs) fabricated on Si wafers. The wider‐bandgap SiGeSn source/drain regions introduce band offsets to the GeSn channel, enabling heterostructure band engineering for leakage suppression and tunneling‐pathway control. Compared with all‐GeSn reference devices, the SiGeSn source/drain architecture suppresses drain‐induced barrier lowering and off‐state leakage without modifying the GeSn channel. The same heterostructure platform also enables complementary TFET operation, where the n‐TFET exhibits a subthreshold swing of 60 mV dec − 1 and a two‐order‐of‐magnitude enhancement in on/off current ratio. The performance difference between p‐ and n‐TFETs provides experimental evidence of the different efficiencies of indirect Γ‐to‐L and direct Γ‐to‐Γ tunneling processes. These results demonstrate that SiGeSn/GeSn heterostructures can be used to suppress leakage currents and engineer tunneling pathways, establishing SiGeSn/GeSn heterostructures as a unified Group‐IV platform for future energy‐efficient CMOS technologies beyond conventional Si.
- Open Access
- 26 September 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Selected Topics in Quantum Electronics
- Vol. PP (1077260X) , 1-15
Monolithically Integrated Optical Through-Silicon Waveguides for 3D Chip-to-Chip Photonic Interconnects
The scaling limitations of electrical interconnects are driving the demand for efficient optical chip-to-chip links. We report the first monolithic integration of air-clad optical through-silicon waveguides in silicon, fabricated via Bosch and cryogenic deep reactive-ion etching. Rib, single-bridge, and double-bridge designs with 50 μm cores and up to 150 μm propagation lengths have been evaluated. Cryogenic-etched rib waveguides achieve the highest median transmission (66%, -1.80 dB), compared to Bosch-etched ribs (62%, -2.08 dB). Across all geometries, 3 dB alignment windows range from 9.3 μm to 49.2 μm, with Bosch-etched double-bridge waveguides providing the broadest tolerance. We show that geometric fidelity outweighs sidewall roughness for transmission and alignment in these large-core, multimode optical through-silicon waveguides. This technology provides a scalable, complementary metal-oxide semiconductor-compatible pathway toward 3D photonic interconnects.
- 26 September 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Selected Topics in Quantum Electronics
- Vol. PP (1077260X) , 1-15
Open AccessMonolithically Integrated Optical Through-Silicon Waveguides for 3D Chip-to-Chip Photonic Interconnects
The scaling limitations of electrical interconnects are driving the demand for efficient optical chip-to-chip links. We report the first monolithic integration of air-clad optical through-silicon waveguides in silicon, fabricated via Bosch and cryogenic deep reactive-ion etching. Rib, single-bridge, and double-bridge designs with 50 μm cores and up to 150 μm propagation lengths have been evaluated. Cryogenic-etched rib waveguides achieve the highest median transmission (66%, -1.80 dB), compared to Bosch-etched ribs (62%, -2.08 dB). Across all geometries, 3 dB alignment windows range from 9.3 μm to 49.2 μm, with Bosch-etched double-bridge waveguides providing the broadest tolerance. We show that geometric fidelity outweighs sidewall roughness for transmission and alignment in these large-core, multimode optical through-silicon waveguides. This technology provides a scalable, complementary metal-oxide semiconductor-compatible pathway toward 3D photonic interconnects.
- Open Access
- 14 May 2025
- Published by MDPI AG in Nanomaterials
- Vol. 15 (10) , 733
Processing and Characterization of High-Density Fe-Silicide/Si Core–Shell Quantum Dots for Light Emission
Si-based photonics has garnered considerable attention as a future device for complementary metal–oxide–semiconductor (CMOS) computing. However, few studies have investigated Si-based light sources highly compatible with Si ultra large-scale integration processing. In this study, we observed stable light emission at room temperature from superatom-like β–FeSi2–core/Si–shell quantum dots (QDs). The β–FeSi2–core/Si–shell QDs, with an areal density as high as ~1011 cm−2 were fabricated by self-aligned silicide process of Fe–silicide capped Si–QDs on ~3.0 nm SiO2/n–Si (100) substrates, followed by SiH4 exposure at 400 °C. From the room temperature photoluminescence characteristics, β–FeSi2 core/Si–shell QDs can be regarded as active elements in optical applications because they offer the advantages of photonic signal processing capabilities and can be combined with electronic logic control and data storage.
- 14 May 2025
- Published by MDPI AG in Nanomaterials
- Vol. 15 (10) , 733
Open AccessProcessing and Characterization of High-Density Fe-Silicide/Si Core–Shell Quantum Dots for Light Emission
Si-based photonics has garnered considerable attention as a future device for complementary metal–oxide–semiconductor (CMOS) computing. However, few studies have investigated Si-based light sources highly compatible with Si ultra large-scale integration processing. In this study, we observed stable light emission at room temperature from superatom-like β–FeSi2–core/Si–shell quantum dots (QDs). The β–FeSi2–core/Si–shell QDs, with an areal density as high as ~1011 cm−2 were fabricated by self-aligned silicide process of Fe–silicide capped Si–QDs on ~3.0 nm SiO2/n–Si (100) substrates, followed by SiH4 exposure at 400 °C. From the room temperature photoluminescence characteristics, β–FeSi2 core/Si–shell QDs can be regarded as active elements in optical applications because they offer the advantages of photonic signal processing capabilities and can be combined with electronic logic control and data storage.
- Open Access
- 20 November 2024
- Published by Springer Nature in The European Physical Journal B
- Vol. 97 (11) , 1-9
Optimization of technology processes for enhanced CMOS-integrated 1T-1R RRAM device performance
Implementing artificial synapses that emulate the synaptic behavior observed in the brain is one of the most critical requirements for neuromorphic computing. Resistive random-access memories (RRAM) have been proposed as a candidate for artificial synaptic devices. For this applicability, RRAM device performance depends on the technology used to fabricate the metal–insulator–metal (MIM) stack and the technology chosen for the selector device. To analyze these dependencies, the integrated RRAM devices in a 4k-bit array are studied on a 200 mm wafer scale in this work. The RRAM devices are integrated into two different CMOS transistor technologies of IHP, namely 250 nm and 130 nm and the devices are compared in terms of their pristine state current. The devices in 130 nm technology have shown lower number of high pristine state current devices per die in comparison to the 250 nm technology. For the 130 nm technology, the forming voltage is reduced due to the decrease of $$\hbox {HfO}_2$$ dielectric thickness from 8 nm to 5 nm. Additionally, 5% Al-doped 4 nm $$\hbox {HfO}_2$$ dielectric displayed a similar reduction in forming voltage and a lower variation in the values. Finally, the multi-level switching between the dielectric layers in 250 nm and 130 nm technologies are compared, where 130 nm showed a more significant number of conductance levels of seven compared to only four levels observed in 250 nm technology. Graphical- 20 November 2024
- Published by Springer Nature in The European Physical Journal B
- Vol. 97 (11) , 1-9
Open AccessOptimization of technology processes for enhanced CMOS-integrated 1T-1R RRAM device performance
Implementing artificial synapses that emulate the synaptic behavior observed in the brain is one of the most critical requirements for neuromorphic computing. Resistive random-access memories (RRAM) have been proposed as a candidate for artificial synaptic devices. For this applicability, RRAM device performance depends on the technology used to fabricate the metal–insulator–metal (MIM) stack and the technology chosen for the selector device. To analyze these dependencies, the integrated RRAM devices in a 4k-bit array are studied on a 200 mm wafer scale in this work. The RRAM devices are integrated into two different CMOS transistor technologies of IHP, namely 250 nm and 130 nm and the devices are compared in terms of their pristine state current. The devices in 130 nm technology have shown lower number of high pristine state current devices per die in comparison to the 250 nm technology. For the 130 nm technology, the forming voltage is reduced due to the decrease of $$\hbox {HfO}_2$$ dielectric thickness from 8 nm to 5 nm. Additionally, 5% Al-doped 4 nm $$\hbox {HfO}_2$$ dielectric displayed a similar reduction in forming voltage and a lower variation in the values. Finally, the multi-level switching between the dielectric layers in 250 nm and 130 nm technologies are compared, where 130 nm showed a more significant number of conductance levels of seven compared to only four levels observed in 250 nm technology. Graphical - 22 December 2023
- Published by The Electrochemical Society in ECS Meeting Abstracts
- Vol. MA2023-02 (30) , 1543
(Invited) Optical Biosensors in Photonic Integrated Circuits for Smart System Integration
Photonic integrated circuits (PIC) are like electronic integrated circuits drivers of communication systems. Moreover, state-of-the-art technologies enable the fabrication of electronic-photonic integrated circuits (ePIC), which allows for example the cointegration of ultra-fast BiCMOS devices with high speed photo detectors. Besides that, this technology provides an attractive platform for biosensors. They open the door for label-free detection of various analytes with high specificity and in real-time. This gives perspective to highly scalable and cost effective technologies for smart system integration of biosensors and electronic readouts to realize a true lab-on-a-chip application. We present the integration of optical biosensors in a Si-based PIC-technology. This comprises a front-end of line with optical waveguides, an integrated Ge-photodiode and a complete back-end of line consisting of three thin and two thick aluminum metal layers. The optical biosensor is integrated by opening the optical waveguide from the backside of the chip. In particular, we released a Si-based slot waveguide, which provides an enhanced evanescent field to interact with the analyte and hence to increase the sensitivity. The slot waveguide is incorporated in a ring resonator and we analyzed the wafer-level performance using the full width at half maximum, which allows us to assess the optical losses. Thermal sensing in a wide temperature range is investigated. In addition, a simple and cost-effective microfluidic is realized and we show initial results of the surface functionalization. Our work demonstrates the compatibility of a photonic biosensor with a photonic integrated circuit technology without any restriction to the standard FEOL and BEOL processing on the wafer front-side, while it keeps the inherent high sensitivity of evanescent-field sensing and opens a route towards smart system integration. Figure 1
- 22 December 2023
- Published by The Electrochemical Society in ECS Meeting Abstracts
- Vol. MA2023-02 (30) , 1543
(Invited) Optical Biosensors in Photonic Integrated Circuits for Smart System Integration
Photonic integrated circuits (PIC) are like electronic integrated circuits drivers of communication systems. Moreover, state-of-the-art technologies enable the fabrication of electronic-photonic integrated circuits (ePIC), which allows for example the cointegration of ultra-fast BiCMOS devices with high speed photo detectors. Besides that, this technology provides an attractive platform for biosensors. They open the door for label-free detection of various analytes with high specificity and in real-time. This gives perspective to highly scalable and cost effective technologies for smart system integration of biosensors and electronic readouts to realize a true lab-on-a-chip application. We present the integration of optical biosensors in a Si-based PIC-technology. This comprises a front-end of line with optical waveguides, an integrated Ge-photodiode and a complete back-end of line consisting of three thin and two thick aluminum metal layers. The optical biosensor is integrated by opening the optical waveguide from the backside of the chip. In particular, we released a Si-based slot waveguide, which provides an enhanced evanescent field to interact with the analyte and hence to increase the sensitivity. The slot waveguide is incorporated in a ring resonator and we analyzed the wafer-level performance using the full width at half maximum, which allows us to assess the optical losses. Thermal sensing in a wide temperature range is investigated. In addition, a simple and cost-effective microfluidic is realized and we show initial results of the surface functionalization. Our work demonstrates the compatibility of a photonic biosensor with a photonic integrated circuit technology without any restriction to the standard FEOL and BEOL processing on the wafer front-side, while it keeps the inherent high sensitivity of evanescent-field sensing and opens a route towards smart system integration. Figure 1
- 7 September 2023
- Published by Japan Society of Applied Physics
Vertical Gate-All-Around SiGeSn/GeSn/SiGeSn Nanowire nFETs
2023 International Conference on Solid State Devices and Materials ,Vertical Gate-All-Around SiGeSn/GeSn/SiGeSn Nanowire nFETs
- 7 September 2023
- Published by Japan Society of Applied Physics
Vertical Gate-All-Around SiGeSn/GeSn/SiGeSn Nanowire nFETs
2023 International Conference on Solid State Devices and Materials ,Vertical Gate-All-Around SiGeSn/GeSn/SiGeSn Nanowire nFETs
- Open Access
- 4 November 2022
- Published by Elsevier in Results in Optics
- Vol. 9
From Lab-on-chip to Lab-in-App: Challenges towards silicon photonic biosensors product developments
- 4 November 2022
- Published by Elsevier in Results in Optics
- Vol. 9
Open AccessFrom Lab-on-chip to Lab-in-App: Challenges towards silicon photonic biosensors product developments
- Open Access
- 29 June 2022
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Microwave Theory and Techniques
- Vol. 70 (11) , 5141-5158
Integrated Millimeter-Wave and Terahertz Analyzers for Biomedical Applications
This invited paper reviews the progress of silicon-based integrated analyzers for biomedical applications over the last two decades. Focus is set on various integrated circuit realizations in the millimeter-wave range from 30 GHz and at the terahertz frequencies of above 300 GHz. This article discusses high-frequency architectures and concrete implementations of both narrowband as well as broadband integrated readout circuits, including their use in miniaturized sensor solutions. A variety of circuits ranging from low-power sensing oscillators to highly integrated broadband vector network analyzers (VNAs), and example realizations of millimeter-wave cardiovascular sensors and implants to THz microfluidic labs-on-chip and exhaled human breath analyzers are recapitulated. This article closes with an outlook on emerging fields of research for future advancement of such biomedical sensors toward reliable and specific systems.
- 29 June 2022
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Microwave Theory and Techniques
- Vol. 70 (11) , 5141-5158
Open AccessIntegrated Millimeter-Wave and Terahertz Analyzers for Biomedical Applications
This invited paper reviews the progress of silicon-based integrated analyzers for biomedical applications over the last two decades. Focus is set on various integrated circuit realizations in the millimeter-wave range from 30 GHz and at the terahertz frequencies of above 300 GHz. This article discusses high-frequency architectures and concrete implementations of both narrowband as well as broadband integrated readout circuits, including their use in miniaturized sensor solutions. A variety of circuits ranging from low-power sensing oscillators to highly integrated broadband vector network analyzers (VNAs), and example realizations of millimeter-wave cardiovascular sensors and implants to THz microfluidic labs-on-chip and exhaled human breath analyzers are recapitulated. This article closes with an outlook on emerging fields of research for future advancement of such biomedical sensors toward reliable and specific systems.