Memristor FPGA IP Core Implementation for Analog and Digital Applications
Authors:
- Mohammed F. TolbaMTMohammed F. Tolba
- Mohammed E. FoudaMFMohammed E. Fouda
- Haneen G. HezayyinHHHaneen G. Hezayyin
- Ahmed H. MadianAMAhmed H. Madian
- Ahmed G. RadwanARAhmed G. Radwan
- 20 November 2018
- journal article
- research article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Circuits and Systems II: Express Briefs
- Vol. 66 (8) , 1381-1385
Abstract
No abstract availableKeywords
This publication has 24 references indexed in Scilit:
- FPGA realization of multi-scroll chaotic oscillatorsCommunications in Nonlinear Science and Numerical Simulation, 2015
- Memristor emulator based on practical current controlled model2015
- Memristor PUF—A Security Primitive: Theory and ExperimentIEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2015
- Digital model of TiO 2 memristor for field‐programmable gate arrayThe Journal of Engineering, 2014
- Memristor Crossbar-Based Neuromorphic Computing System: A Case StudyIEEE Transactions on Neural Networks and Learning Systems, 2014
- A chaotic circuit based on Hewlett-Packard memristorChaos: An Interdisciplinary Journal of Nonlinear Science, 2012
- Anatomy of a Nanoscale Conduction Channel Reveals the Mechanism of a High‐Performance MemristorAdvanced Materials, 2011
- Experimental demonstration of associative memory with memristive neural networksNeural Networks, 2010
- IMPLEMENTING MEMRISTOR BASED CHAOTIC CIRCUITSInternational Journal of Bifurcation and Chaos, 2010
- Nanoscale Memristor Device as Synapse in Neuromorphic SystemsNano Letters, 2010