A 14 b 35 MS/s SAR ADC Achieving 75 dB SNDR and 99 dB SFDR With Loop-Embedded Input Buffer in 40 nm CMOS

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Abstract
This paper presents a 14 bit 35 MS/s successive approximation register (SAR) ADC that achieves a nearly constant 74.5 dB peak SNDR up to Nyquist and an SFDR of 90/99 dB for inputs near Nyquist and at low-frequencies, respectively. The ADC employs a loop-embedded input buffer that shields the large sampling capacitor from the input and thereby eases the ADC drive requirements significantly. Since the buffer's nonlinearity is cancelled by the SAR operation, a pair of basic source followers can be used, adding only 12.5 mW (23% of the total power) to the power budget. The ADC includes a bandgap reference and a self-calibrated current steering DAC to close the SAR loop, which eliminates the need for a low-impedance off-chip reference. The design occupies 0.236 mm 2 in 40 nm CMOS and consumes a total power of 54.5 mW from its 1.2/2.5 V supplies, leading to an SNDR-based Schreier FOM of 159.5 dB at Nyquist.

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