A PVT insensitive field programmable gate array time-to-digital converter
Authors:
- Poki ChenPCPoki Chen
- Hsiu Che ChengHCHsiu Che Cheng
- Arif WidodoAWArif Widodo
- Wei Xiang TsaiWTWei Xiang Tsai
- 1 October 2013
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1-4
Abstract
A process, voltage and temperature (PVT) insensitive time-to-digital converter (TDC) implemented in field programmable gate array (FPGA) is presented. The aim is to provide a PVT insensitive TDC solution with god enough resolution and wide measurement range. With the aid of FPGA embedded phase locked loop (PLL) which provides eight different output phases, a constant resolution around 84 ps can be ensured. The short term differential nonlinearity (DNL) is measured to be -0.482 ~ 0.457 LSB, and the corresponding integral nonlinearity (INL) is merely -0.612 ~ 0.575 LSB. This TDC was tested to be fully functional over 0°C to 50°C ambient temperature ranges with extremely low variation on resolution.Keywords
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