Comparison of Fixed Switching Frequency FCS-MPC Strategies Applied to a Multilevel Converter: A Case Study of a Hybrid Cascade Converter Based on 2L-VSI and H-Bridge Converters

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Abstract
This paper evaluates the performance of strategies based on finite-control-set model predictive control (FCS-MPC) aimed at reducing or fixing the converter switching frequency or decreasing the spread of the harmonic spectrum in multilevel hybrid cascade converters (HCCs). These properties are desirable for medium- to high-voltage applications, where minimizing switching losses is crucial, as well as for applications employing passive filters, where resonance modes can be excited. The strategies evaluated are input restriction, notch filtering, period control, and PWM restriction. Key aspects considered in this work are (i) the evaluation of the steady-state and transient performance of FCS-MPC strategies proposed for two-level converters in a multilevel topology, and (ii) the evaluation of the computational cost associated with the implementation of these strategies on a multilevel converter with a high number of available inputs. As a typical application, the study is carried out employing a five-level HCC experimental prototype driving an induction motor through indirect vector control. To perform a fair comparison between the strategies, a control platform based on a cost-effective Zynq system on chip is proposed, which allows for achieving the hard timing constraints imposed by FCS-MPC strategies. The results show that the PWM restriction strategy achieves the best steady-state performance among the evaluated strategies, with an error 400 times smaller than that of the second-best strategy (input restriction), with an average switching frequency of 962.5 Hz, which differs from the desired average frequency by 3%, and a maximum difference in power distribution between modules of 0.8%. In addition, the system-on-chip hardware achieves a competitive execution time of 46 μs when the ARM Cortex solution is implemented and 20 μs when the ARM Cortex–FPGA solution is used instead, employing the 512 inputs available in the FCS-MPC algorithm. The studies, performed in steady-state and transient regimes, confirm (i) the feasibility of the evaluated algorithms in an HCC topology and (ii) the feasibility of the control platform for implementing high-computational-burden algorithms with a low sampling time.
Funding Information
  • Comisión Nacional de Investigación Científica y Tecnológica (11241077)

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