Characterization and Stabilization of Short-Term Fluctuations in the Analog Conductance States of Ta/Ta 2 O 5-x ReRAM
Authors:
- Ryan C. DempseyRDRyan C. Dempsey
- Matthew SpearMSMatthew Spear
- T. Patrick XiaoTXT. Patrick Xiao
- William WahbyWWWilliam Wahby
- Robin Jacobs-GedrimRJRobin Jacobs-Gedrim
- Eduardo OrtegaEOEduardo Ortega
- Christopher BennettCBChristopher Bennett
- Sapan AgarwalSASapan Agarwal
- Matthew J. MarinellaMMMatthew J. Marinella
- 5 November 2025
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 72 (12) , 6699-6707
Abstract
Analog in-memory computing (AIMC) utilizing nonvolatile resistive memory arrays can drastically reduce the energy required for neural network inference. The oxide-based resistive random access memory (ReRAM) devices are a promising candidate for AIMC due to their high density and ability to store multiple bits of precision in an analog state. However, variability in conductance fluctuations across devices and programming cycles in each device presents a challenge for inference accuracy. We characterize the signature of conductance fluctuations in a Ta/Ta2O5-x ReRAM array, finding significant variability in fluctuations from cycle-to-cycle associated with different filament configurations, which ultimately causes high conductance variability at the conclusion of the settling period of $\approx 1$ h following programming. Although cycle-to-cycle variability and device-to-device fluctuation variability were similar, specific devices tended toward high cycle-to-cycle variability. Most devices had an optimal filamentary configuration, which was relatively stable over time. By creating a smart write-verify routine, which determines the optimal filament configuration, it was possible to improve the inference accuracy for CIFAR-10 image recognition from 28.5% to 79.1% as measured following the 1-h settling period.Keywords
Funding Information
- Sandia’s Laboratory Directed Research and Development (LDRD) program
- Microelectronics Commons Program, a Department of War Initiative (N00164-23-9-G030)
- Aerospace Internal Research and Development Funding
This publication has 26 references indexed in Scilit:
- Using the IBM analog in-memory hardware acceleration kit for neural network training and inferenceAPL Machine Learning, 2023
- Thousands of conductance levels in memristors integrated on CMOSNature, 2023
- A compute-in-memory chip based on resistive random-access memoryNature, 2022
- Nanoionic memristive phenomena in metal oxides: the valence change mechanismAdvances in Physics, 2021
- Analog architectures for neural network acceleration based on non-volatile memoryApplied Physics Reviews, 2020
- Accurate deep neural network inference using computational phase-change memoryNature Communications, 2020
- Noise in Resistive Random Access Memory Devices2020
- In-memory computing with resistive switching devicesNature Electronics, 2018
- Subfilamentary Networks Cause Cycle-to-Cycle Variability in Memristive DevicesACS Nano, 2017
- Random telegraph noise and resistance switching analysis of oxide based resistive memoryNanoscale, 2013