Matthew J. Marinella

This work investigates how thinning the Si substrate alters the single event upset (SEU) response of 6T SRAM cells fab-ricated in a bulk 28 nm CMOS process technology. Previously published results on bulk 0.6 μm CMOS process SRAM cells showed that thinning provides significant hardening against SEU. Laser raster-scan data, heavy-ion data, and TCAD SEU simula-tions are all in qualitative agreement that thinning the 28 nm pro-cess SRAM cells increases SEU susceptibility. TCAD analysis demonstrates that thinning triggers the parasitic bipolar junction transistor (BJT) mechanism prompted by the ion-strike and that this mechanism is enhanced by substate thinning. Thinning in-creases the resistance at the region connecting the base of the built-in parasitic BJT to the body electrode. Therefore, the potential in the base, caused by ion-generated hole transport out of the body region is higher in the thinner case, enabling a hole current out of the NFET via the body electrode. This higher potential in the par-asitic BJT “base” region enables greater forward-biasing at the source(emitter)/body(base) junction. Thus, the thinner case has more back-injected electrons from the emitter when compared to the thicker case. These excess electrons lead to greater charge col-lection at the sensitive drain nodes of the SRAM. The simulated linear energy transfer thresholds (LET_TH) are slightly less for the thinner parts which correlates to laser and heavy ion data.

Resistive random-access memory (RRAM)-based in-memory computing (R-IMC) architectures achieve energy efficiency by avoiding data movement for matrix-vector computation. However, R-IMC suffers from reliability challenges, such as programming errors, conductance drift, and stuck-at faults, which introduce noise and degrade performance. Several approaches have been proposed in the literature to enhance reliability; however, these solutions are limited to a few specific types of non-idealities, and they cannot be applied to large models, pre-trained models, or R-IMC architectures without introducing considerable computation and memory overhead. We propose a design-time solution that uses a mixture of fault-tolerant experts by adapting pre-trained models via low-rank adaptation. We train non-idealities-specific experts, which are merged with the base weights before mapping, ensuring no added cost yet reliable R-IMC inferencing. For a range of vision and language tasks with transformer models, we show that our approach improves inferencing accuracy by up to 76% under a mixture of non-idealities, enabling reliable mapping and inferencing of vision–language models with no additional cost at runtime.

Analog in-memory computing (AIMC) utilizing nonvolatile resistive memory arrays can drastically reduce the energy required for neural network inference. The oxide-based resistive random access memory (ReRAM) devices are a promising candidate for AIMC due to their high density and ability to store multiple bits of precision in an analog state. However, variability in conductance fluctuations across devices and programming cycles in each device presents a challenge for inference accuracy. We characterize the signature of conductance fluctuations in a Ta/Ta₂O_5-x ReRAM array, finding significant variability in fluctuations from cycle-to-cycle associated with different filament configurations, which ultimately causes high conductance variability at the conclusion of the settling period of $\approx 1$ h following programming. Although cycle-to-cycle variability and device-to-device fluctuation variability were similar, specific devices tended toward high cycle-to-cycle variability. Most devices had an optimal filamentary configuration, which was relatively stable over time. By creating a smart write-verify routine, which determines the optimal filament configuration, it was possible to improve the inference accuracy for CIFAR-10 image recognition from 28.5% to 79.1% as measured following the 1-h settling period.

Electrochemical random-access memory (ECRAM) is an emerging three-terminal nonvolatile memory with highly controllable channel conductance, and hence is promising for use as an analog memory (or synapse) in analog in-memory computing (AIMC) systems. Energy efficient AIMC computing is particularly desirable for power-constrained, high radiation environments such as satellites. However, little is known about the suitability of ECRAM for use in a total ionizing dose (TID) environment. This work investigates the effect of Co-60 gamma radiation on the channel conductance and noise - two properties critical for AIMC systems - of a TaO_x-based ECRAM up to 17.3 Mrad(SiO₂) for both low and high channel conductance state devices. A transient increase in conductance is observed in response to radiation which consists of two elements: an immediate increase photoconductivity and a secondary photocurrent, which has a slower rise and saturation and can persist for hours after exposure and is attributed to charging due to hole trapping. These transient effects would not likely occur in a space environment due to the low dose rate. No permanent change is found in the low conductance state following exposure and the minor shift in the high conductance change would be less significant than the regular retention decay in this state. A permanent increase in the random telegraph noise is observed, possibly due to increased traps created in the channel. This work demonstrates that TaO_xbased ECRAM is suitable for use in spaceborne AIMC systems that are subject to significant TID.

Silicon-oxide-nitride-oxide-silicon (SONOS) charge-trap memory is a promising nonvolatile memory device for analog in-memory computing applications. The sensitivity of 40nm SONOS analog states in response to single event effects (SEE) were experimentally assessed by exposing a SONOS array to heavy ions with LET’s of 28.6, 44.9, and 59.5 MeV/(mg/cm²). A statistical model of SEE was developed using specific criteria to distinguish them from effects unrelated to radiation, such as device-to-device programming variation, read noise, and drift. This model was used to simulate the effects of heavy ions on an analog in-memory computing (AIMC) accelerator processing standard deep neural networks running inference on common datasets, including ImageNet. Simulated inference accuracy decreases with increasing LET and fluence. At the highest LET of 59.5 MeV-cm²/mg, an accuracy degradation of 5% on ImageNet was predicted at a fluence of 3x10⁶ ions/cm², indicating a sufficient performance for most space applications.